changeset 7b99564233cd in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=7b99564233cd
description:
inorder: inst count mgmt
diffstat:
14 files changed, 210 insertions(+), 67 deletions(-)
src/cpu/inorder/SConscript | 2
src/cpu/inorder/cpu.cc | 38 +++++----
src/cpu/inorder/cpu.hh | 2
src/cpu/inorder/inorder_dyn_inst.cc | 8 +-
src/cpu/inorder/inorder_dyn_inst.hh | 5 -
src/cpu/inorder/pipeline_stage.cc | 26 +++++-
src/cpu/inorder/reg_dep_map.cc | 24 ++++++
src/cpu/inorder/reg_dep_map.hh | 2
src/cpu/inorder/resource.cc | 34 +++++---
src/cpu/inorder/resource.hh | 11 ++
src/cpu/inorder/resources/cache_unit.cc | 103 +++++++++++++++++++-------
src/cpu/inorder/resources/cache_unit.hh | 5 -
src/cpu/inorder/resources/graduation_unit.cc | 2
src/cpu/inorder/resources/use_def.cc | 15 +++
diffs (truncated from 700 to 300 lines):
diff -r de51ab31b456 -r 7b99564233cd src/cpu/inorder/SConscript
--- a/src/cpu/inorder/SConscript Sun Jan 31 18:30:43 2010 -0500
+++ b/src/cpu/inorder/SConscript Sun Jan 31 18:30:48 2010 -0500
@@ -54,6 +54,8 @@
TraceFlag('InOrderGraduation')
TraceFlag('ThreadModel')
TraceFlag('RefCount')
+ TraceFlag('AddrDep')
+
CompoundFlag('InOrderCPUAll', [ 'InOrderStage', 'InOrderStall',
'InOrderCPU',
'InOrderMDU', 'InOrderAGEN', 'InOrderFetchSeq', 'InOrderTLB',
'InOrderBPred',
diff -r de51ab31b456 -r 7b99564233cd src/cpu/inorder/cpu.cc
--- a/src/cpu/inorder/cpu.cc Sun Jan 31 18:30:43 2010 -0500
+++ b/src/cpu/inorder/cpu.cc Sun Jan 31 18:30:48 2010 -0500
@@ -333,6 +333,12 @@
0);
}
+ dummyReqInst = new InOrderDynInst(this, NULL, 0, 0, 0);
+ dummyReqInst->setSquashed();
+
+ dummyBufferInst = new InOrderDynInst(this, NULL, 0, 0, 0);
+ dummyBufferInst->setSquashed();
+
lastRunningCycle = curTick;
// Reset CPU to reset state.
@@ -343,6 +349,8 @@
reset();
#endif
+ dummyBufferInst->resetInstCount();
+
// Schedule First Tick Event, CPU will reschedule itself from here on out.
scheduleTickEvent(0);
}
@@ -1176,6 +1184,8 @@
removeInst(inst);
}
+// currently unused function, but substitute repetitive code w/this function
+// call
void
InOrderCPU::addToRemoveList(DynInstPtr &inst)
{
@@ -1194,6 +1204,10 @@
removeInstsThisCycle = true;
// Remove the instruction.
+
+ DPRINTF(RefCount, "Pushing instruction [tid:%i] PC %#x "
+ "[sn:%lli] to remove list\n",
+ inst->threadNumber, inst->readPC(), inst->seqNum);
removeList.push(inst->getInstListIt());
}
@@ -1208,7 +1222,7 @@
inst_iter--;
- DPRINTF(InOrderCPU, "Deleting instructions from CPU instruction "
+ DPRINTF(InOrderCPU, "Squashing instructions from CPU instruction "
"list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
tid, seq_num, (*inst_iter)->seqNum);
@@ -1238,6 +1252,9 @@
(*instIt)->setSquashed();
+ DPRINTF(RefCount, "Pushing instruction [tid:%i] PC %#x "
+ "[sn:%lli] to remove list\n",
+ (*instIt)->threadNumber, (*instIt)->readPC(),
(*instIt)->seqNum);
removeList.push(instIt);
}
}
@@ -1251,7 +1268,7 @@
"[tid:%i] [sn:%lli] PC %#x\n",
(*removeList.front())->threadNumber,
(*removeList.front())->seqNum,
- (*removeList.front())->readPC());
+ (*removeList.front())->readPC());
DynInstPtr inst = *removeList.front();
ThreadID tid = inst->threadNumber;
@@ -1279,11 +1296,6 @@
instList[tid].erase(removeList.front());
removeList.pop();
-
- DPRINTF(RefCount, "pop from remove list: [sn:%i]: Refcount = %i.\n",
- inst->seqNum,
- 0/*inst->curCount()*/);
-
}
removeInstsThisCycle = false;
@@ -1295,22 +1307,18 @@
while (!reqRemoveList.empty()) {
ResourceRequest *res_req = reqRemoveList.front();
- DPRINTF(RefCount, "[tid:%i]: Removing Request, "
- "[sn:%lli] [slot:%i] [stage_num:%i] [res:%s] [refcount:%i].\n",
+ DPRINTF(InOrderCPU, "[tid:%i] [sn:%lli]: Removing Request "
+ "[stage_num:%i] [res:%s] [slot:%i] [completed:%i].\n",
res_req->inst->threadNumber,
res_req->inst->seqNum,
- res_req->getSlot(),
res_req->getStageNum(),
res_req->res->name(),
- 0/*res_req->inst->curCount()*/);
+ (res_req->isCompleted()) ? res_req->getComplSlot() :
res_req->getSlot(),
+ res_req->isCompleted());
reqRemoveList.pop();
delete res_req;
-
- DPRINTF(RefCount, "after remove request: [sn:%i]: Refcount = %i.\n",
- res_req->inst->seqNum,
- 0/*res_req->inst->curCount()*/);
}
}
diff -r de51ab31b456 -r 7b99564233cd src/cpu/inorder/cpu.hh
--- a/src/cpu/inorder/cpu.hh Sun Jan 31 18:30:43 2010 -0500
+++ b/src/cpu/inorder/cpu.hh Sun Jan 31 18:30:48 2010 -0500
@@ -247,6 +247,8 @@
/** Instruction used to signify that there is no *real* instruction in
buffer slot */
DynInstPtr dummyInst[ThePipeline::MaxThreads];
+ DynInstPtr dummyBufferInst;
+ DynInstPtr dummyReqInst;
/** Used by resources to signify a denied access to a resource. */
ResourceRequest *dummyReq[ThePipeline::MaxThreads];
diff -r de51ab31b456 -r 7b99564233cd src/cpu/inorder/inorder_dyn_inst.cc
--- a/src/cpu/inorder/inorder_dyn_inst.cc Sun Jan 31 18:30:43 2010 -0500
+++ b/src/cpu/inorder/inorder_dyn_inst.cc Sun Jan 31 18:30:48 2010 -0500
@@ -164,7 +164,7 @@
// Update Instruction Count for this instruction
++instcount;
- if (instcount > 500) {
+ if (instcount > 100) {
fatal("Number of Active Instructions in CPU is too high. "
"(Not Dereferencing Ptrs. Correctly?)\n");
}
@@ -175,6 +175,12 @@
threadNumber, seqNum, instcount);
}
+void
+InOrderDynInst::resetInstCount()
+{
+ instcount = 0;
+}
+
InOrderDynInst::~InOrderDynInst()
{
diff -r de51ab31b456 -r 7b99564233cd src/cpu/inorder/inorder_dyn_inst.hh
--- a/src/cpu/inorder/inorder_dyn_inst.hh Sun Jan 31 18:30:43 2010 -0500
+++ b/src/cpu/inorder/inorder_dyn_inst.hh Sun Jan 31 18:30:48 2010 -0500
@@ -1032,14 +1032,15 @@
/** Count of total number of dynamic instructions. */
static int instcount;
+ void resetInstCount();
+
/** Dumps out contents of this BaseDynInst. */
void dump();
/** Dumps out contents of this BaseDynInst into given string. */
void dump(std::string &outstring);
-
- //inline int curCount() { return curCount(); }
+ //inline int curCount() { return curCount(); }
};
diff -r de51ab31b456 -r 7b99564233cd src/cpu/inorder/pipeline_stage.cc
--- a/src/cpu/inorder/pipeline_stage.cc Sun Jan 31 18:30:43 2010 -0500
+++ b/src/cpu/inorder/pipeline_stage.cc Sun Jan 31 18:30:48 2010 -0500
@@ -101,8 +101,6 @@
{
cpu = cpu_ptr;
- dummyBufferInst = new InOrderDynInst(cpu_ptr, NULL, 0, 0, 0);
-
DPRINTF(InOrderStage, "Set CPU pointer.\n");
tracer = dynamic_cast<Trace::InOrderTrace *>(cpu->getTracer());
@@ -388,6 +386,8 @@
prevStage->insts[i]->seqNum,
prevStage->insts[i]->readPC());
prevStage->insts[i]->setSquashed();
+
+ prevStage->insts[i] = cpu->dummyBufferInst;
}
}
}
@@ -609,7 +609,7 @@
skidBuffer[tid].push(prevStage->insts[i]);
- prevStage->insts[i] = dummyBufferInst;
+ prevStage->insts[i] = cpu->dummyBufferInst;
}
}
@@ -816,7 +816,7 @@
// call processInsts()
// If status is Unblocking,
// buffer any instructions coming from fetch
- // continue trying to empty skid buffer
+ // continue trying to empty skid buffer
// check if stall conditions have passed
// Stage should try to process as many instructions as its bandwidth
@@ -960,6 +960,8 @@
}
reqs_processed++;
+
+ req->stagePasses++;
} else {
DPRINTF(InOrderStage, "[tid:%i]: [sn:%i] request to %s failed."
"\n", tid, inst->seqNum, cpu->resPool->name(res_num));
@@ -969,7 +971,7 @@
if (req->isMemStall() &&
cpu->threadModel == InOrderCPU::SwitchOnCacheMiss) {
// Save Stalling Instruction
- DPRINTF(ThreadModel, "[tid:%i] Detected cache miss.\n",
tid);
+ DPRINTF(ThreadModel, "[tid:%i] [sn:%i] Detected cache
miss.\n", tid, inst->seqNum);
DPRINTF(InOrderStage, "Inserting [tid:%i][sn:%i] into
switch out buffer.\n",
tid, inst->seqNum);
@@ -994,6 +996,20 @@
cpu->activateNextReadyContext();
}
+ // Mark request for deletion
+ // if it isnt currently being used by a resource
+ if (!req->hasSlot()) {
+ DPRINTF(InOrderStage, "[sn:%i] Deleting Request, has no
slot in resource.\n",
+ inst->seqNum);
+
+ cpu->reqRemoveList.push(req);
+ } else {
+ DPRINTF(InOrderStage, "[sn:%i] Ignoring Request Deletion,
in resource [slot:%i].\n",
+ inst->seqNum, req->getSlot());
+ //req = cpu->dummyReq[tid];
+ }
+
+
break;
}
diff -r de51ab31b456 -r 7b99564233cd src/cpu/inorder/reg_dep_map.cc
--- a/src/cpu/inorder/reg_dep_map.cc Sun Jan 31 18:30:43 2010 -0500
+++ b/src/cpu/inorder/reg_dep_map.cc Sun Jan 31 18:30:48 2010 -0500
@@ -235,3 +235,27 @@
return NULL;
}
+
+void
+RegDepMap::dump()
+{
+
+ for (int idx=0; idx < regMap.size(); idx++) {
+
+ if (regMap[idx].size() > 0) {
+ cprintf("Reg #%i (size:%i): ", idx, regMap[idx].size());
+
+ std::list<DynInstPtr>::iterator list_it = regMap[idx].begin();
+ std::list<DynInstPtr>::iterator list_end = regMap[idx].end();
+
+ while (list_it != list_end) {
+ cprintf("[sn:%i] ", (*list_it)->seqNum);
+
+ list_it++;
+ }
+
+ cprintf("\n");
+ }
+
+ }
+}
diff -r de51ab31b456 -r 7b99564233cd src/cpu/inorder/reg_dep_map.hh
--- a/src/cpu/inorder/reg_dep_map.hh Sun Jan 31 18:30:43 2010 -0500
+++ b/src/cpu/inorder/reg_dep_map.hh Sun Jan 31 18:30:48 2010 -0500
@@ -88,6 +88,8 @@
/** Size of Dependency of Map */
int depSize(unsigned idx);
+ void dump();
+
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