changeset a3a20caba701 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a3a20caba701
description:
inorder: update hello world mips
diffstat:
3 files changed, 120 insertions(+), 102 deletions(-)
tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini | 1
tests/quick/00.hello/ref/mips/linux/inorder-timing/simout | 12
tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt | 209 +++++-----
diffs (truncated from 389 to 300 lines):
diff -r d96b8280b306 -r a3a20caba701
tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini
--- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini Sun Jan
31 18:31:20 2010 -0500
+++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini Sun Jan
31 18:31:28 2010 -0500
@@ -117,6 +117,7 @@
stageTracing=false
stageWidth=1
system=system
+threadModel=SMT
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
diff -r d96b8280b306 -r a3a20caba701
tests/quick/00.hello/ref/mips/linux/inorder-timing/simout
--- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout Sun Jan 31
18:31:20 2010 -0500
+++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout Sun Jan 31
18:31:28 2010 -0500
@@ -5,13 +5,13 @@
All Rights Reserved
-M5 compiled Jan 2 2010 07:01:31
-M5 revision a538feb8a617 6813 default qtip tip qbase fixhelp.patch
-M5 started Jan 2 2010 07:03:09
-M5 executing on fajita
-command line: build/MIPS_SE/m5.opt -d
build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing -re
tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing
+M5 compiled Jan 31 2010 17:08:14
+M5 revision 01508015f86b 6964 default qtip tip inorder_hello_mips
+M5 started Jan 31 2010 17:08:15
+M5 executing on zooks
+command line: build/MIPS_SE/m5.fast -d
build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing -re
tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello World!
-Exiting @ tick 29940500 because target called exit()
+Exiting @ tick 29206500 because target called exit()
diff -r d96b8280b306 -r a3a20caba701
tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt
--- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt Sun Jan
31 18:31:20 2010 -0500
+++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt Sun Jan
31 18:31:28 2010 -0500
@@ -1,96 +1,96 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 10400 #
Simulator instruction rate (inst/s)
-host_mem_usage 205896 #
Number of bytes of host memory used
-host_seconds 0.56 #
Real time elapsed on the host
-host_tick_rate 53415864 #
Simulator tick rate (ticks/s)
+host_inst_rate 19644 #
Simulator instruction rate (inst/s)
+host_mem_usage 155856 #
Number of bytes of host memory used
+host_seconds 0.30 #
Real time elapsed on the host
+host_tick_rate 98307932 #
Simulator tick rate (ticks/s)
sim_freq 1000000000000 #
Frequency of simulated ticks
sim_insts 5827 #
Number of instructions simulated
-sim_seconds 0.000030 #
Number of seconds simulated
-sim_ticks 29940500 #
Number of ticks simulated
+sim_seconds 0.000029 #
Number of seconds simulated
+sim_ticks 29206500 #
Number of ticks simulated
system.cpu.AGEN-Unit.instReqsProcessed 2090 #
Number of Instructions Requests that completed in this resource.
system.cpu.Branch-Predictor.instReqsProcessed 5828
# Number of Instructions Requests that completed in this resource.
system.cpu.Branch-Predictor.predictedNotTaken 826
# Number of Branches Predicted As Not Taken (False).
system.cpu.Branch-Predictor.predictedTaken 90
# Number of Branches Predicted As Taken (True).
system.cpu.Decode-Unit.instReqsProcessed 5828 #
Number of Instructions Requests that completed in this resource.
+system.cpu.Execution-Unit.cyclesExecuted 3725 #
Number of Cycles Execution Unit was used.
system.cpu.Execution-Unit.instReqsProcessed 3734
# Number of Instructions Requests that completed in this resource.
system.cpu.Execution-Unit.predictedNotTakenIncorrect 541
# Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.Execution-Unit.predictedTakenIncorrect 35
# Number of Branches Incorrectly Predicted As Taken.
-system.cpu.Fetch-Buffer-T0.instReqsProcessed 0
# Number of Instructions Requests that completed in this resource.
-system.cpu.Fetch-Buffer-T0.instsBypassed 0 #
Number of Instructions Bypassed.
-system.cpu.Fetch-Buffer-T1.instReqsProcessed 0
# Number of Instructions Requests that completed in this resource.
-system.cpu.Fetch-Buffer-T1.instsBypassed 0 #
Number of Instructions Bypassed.
-system.cpu.Fetch-Seq-Unit.instReqsProcessed 11657
# Number of Instructions Requests that completed in this resource.
+system.cpu.Execution-Unit.utilization 0.063769 #
Utilization of Execution Unit (cycles / totalCycles).
+system.cpu.Fetch-Seq-Unit.instReqsProcessed 11702
# Number of Instructions Requests that completed in this resource.
system.cpu.Graduation-Unit.instReqsProcessed 5827
# Number of Instructions Requests that completed in this resource.
system.cpu.Mult-Div-Unit.divInstReqsProcessed 1
# Number of Divide Requests Processed.
system.cpu.Mult-Div-Unit.instReqsProcessed 8
# Number of Instructions Requests that completed in this resource.
system.cpu.Mult-Div-Unit.multInstReqsProcessed 3
# Number of Multiply Requests Processed.
system.cpu.RegFile-Manager.instReqsProcessed 10713
# Number of Instructions Requests that completed in this resource.
+system.cpu.activity 20.277673 #
Percentage of cycles cpu is active
system.cpu.committedInsts 5827 #
Number of Instructions Simulated (Per-Thread)
system.cpu.committedInsts_total 5827 #
Number of Instructions Simulated (Total)
-system.cpu.cpi 10.276643 #
CPI: Cycles Per Instruction (Per-Thread)
-system.cpu.cpi_total 10.276643 #
CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 1165 #
number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 56201.149425
# average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53201.149425
# average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 1078 #
number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 4889500 #
number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.074678 #
miss rate for ReadReq accesses
+system.cpu.contextSwitches 1 #
Number of context switches
+system.cpu.cpi 10.024713 #
CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi_total 10.024713 #
CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 1164 #
number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 56229.885057
# average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53229.885057
# average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 1077 #
number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 4892000 #
number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.074742 #
miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 87 #
number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 4628500
# number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.074678 #
mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency 4631000
# number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.074742 #
mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 87 #
number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 925 #
number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 56554.687500
# average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53554.687500
# average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 56265.625000
# average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53265.625000
# average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 861 #
number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 3619500 #
number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 3601000 #
number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.069189 #
miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 64 #
number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 3427500
# number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 3409000
# number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.069189 #
mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 64 #
number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
# average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value
# average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 14.144928 #
Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 14.137681 #
Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 #
number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 #
number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0
# number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0
# number of cycles access was blocked
system.cpu.dcache.cache_copies 0 #
number of cache copies performed
-system.cpu.dcache.demand_accesses 2090 #
number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 56350.993377 #
average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 53350.993377
# average overall mshr miss latency
-system.cpu.dcache.demand_hits 1939 #
number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 8509000 #
number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.072249 #
miss rate for demand accesses
+system.cpu.dcache.demand_accesses 2089 #
number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 56245.033113 #
average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 53245.033113
# average overall mshr miss latency
+system.cpu.dcache.demand_hits 1938 #
number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 8493000 #
number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.072283 #
miss rate for demand accesses
system.cpu.dcache.demand_misses 151 #
number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 #
number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 8056000
# number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.072249 #
mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_latency 8040000
# number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.072283 #
mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 151 #
number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 #
number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 #
number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 #
Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 2090 #
number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 56350.993377
# average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 53350.993377
# average overall mshr miss latency
+system.cpu.dcache.overall_accesses 2089 #
number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 56245.033113
# average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 53245.033113
# average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value
# average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 1939 #
number of overall hits
-system.cpu.dcache.overall_miss_latency 8509000 #
number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.072249 #
miss rate for overall accesses
+system.cpu.dcache.overall_hits 1938 #
number of overall hits
+system.cpu.dcache.overall_miss_latency 8493000 #
number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.072283 #
miss rate for overall accesses
system.cpu.dcache.overall_misses 151 #
number of overall misses
system.cpu.dcache.overall_mshr_hits 0 #
number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 8056000
# number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.072249 #
mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_latency 8040000
# number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.072283 #
mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 151 #
number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0
# number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0
# number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 0 #
number of replacements
system.cpu.dcache.sampled_refs 138 #
Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 #
number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 88.212490 #
Cycle average of tags in use
-system.cpu.dcache.total_refs 1952 #
Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 88.491296 #
Cycle average of tags in use
+system.cpu.dcache.total_refs 1951 #
Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 #
Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 #
number of writebacks
system.cpu.dcache_port.instReqsProcessed 2089 #
Number of Instructions Requests that completed in this resource.
@@ -103,62 +103,63 @@
system.cpu.dtb.write_accesses 0 #
DTB write accesses
system.cpu.dtb.write_hits 0 #
DTB write hits
system.cpu.dtb.write_misses 0 #
DTB write misses
-system.cpu.icache.ReadReq_accesses 5829 #
number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 55765.676568
# average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 52765.676568
# average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 5526 #
number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 16897000 #
number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.051981 #
miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_accesses 5874 #
number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 55801.980198
# average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 52801.980198
# average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 5571 #
number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 16908000 #
number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.051583 #
miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 303 #
number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 15988000
# number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.051981 #
mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_latency 15999000
# number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.051583 #
mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 303 #
number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
# average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value
# average number of cycles each access was blocked
-system.cpu.icache.avg_refs 18.237624 #
Average number of references to valid blocks.
+system.cpu.icache.avg_refs 18.386139 #
Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 #
number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 #
number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0
# number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0
# number of cycles access was blocked
system.cpu.icache.cache_copies 0 #
number of cache copies performed
-system.cpu.icache.demand_accesses 5829 #
number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 55765.676568 #
average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 52765.676568
# average overall mshr miss latency
-system.cpu.icache.demand_hits 5526 #
number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 16897000 #
number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.051981 #
miss rate for demand accesses
+system.cpu.icache.demand_accesses 5874 #
number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 55801.980198 #
average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 52801.980198
# average overall mshr miss latency
+system.cpu.icache.demand_hits 5571 #
number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 16908000 #
number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.051583 #
miss rate for demand accesses
system.cpu.icache.demand_misses 303 #
number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 #
number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 15988000
# number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.051981 #
mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_latency 15999000
# number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.051583 #
mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 303 #
number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 #
number of fast writes performed
system.cpu.icache.mshr_cap_events 0 #
number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 #
Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 5829 #
number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 55765.676568
# average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 52765.676568
# average overall mshr miss latency
+system.cpu.icache.overall_accesses 5874 #
number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 55801.980198
# average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 52801.980198
# average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value
# average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 5526 #
number of overall hits
-system.cpu.icache.overall_miss_latency 16897000 #
number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.051981 #
miss rate for overall accesses
+system.cpu.icache.overall_hits 5571 #
number of overall hits
+system.cpu.icache.overall_miss_latency 16908000 #
number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.051583 #
miss rate for overall accesses
system.cpu.icache.overall_misses 303 #
number of overall misses
system.cpu.icache.overall_mshr_hits 0 #
number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 15988000
# number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.051981 #
mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_latency 15999000
# number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.051583 #
mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 303 #
number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0
# number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0
# number of overall MSHR uncacheable misses
system.cpu.icache.replacements 13 #
number of replacements
system.cpu.icache.sampled_refs 303 #
Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 #
number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 134.267603 #
Cycle average of tags in use
-system.cpu.icache.total_refs 5526 #
Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 135.362853 #
Cycle average of tags in use
+system.cpu.icache.total_refs 5571 #
Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 #
Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 #
number of writebacks
-system.cpu.icache_port.instReqsProcessed 5828 #
Number of Instructions Requests that completed in this resource.
-system.cpu.ipc 0.097308 #
IPC: Instructions Per Cycle (Per-Thread)
-system.cpu.ipc_total 0.097308 #
IPC: Total IPC of All Threads
+system.cpu.icache_port.instReqsProcessed 5873 #
Number of Instructions Requests that completed in this resource.
+system.cpu.idleCycles 46569 #
Number of cycles cpu's stages were not processed
+system.cpu.ipc 0.099753 #
IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.ipc_total 0.099753 #
IPC: Total IPC of All Threads
system.cpu.itb.accesses 0 #
DTB accesses
system.cpu.itb.hits 0 #
DTB hits
system.cpu.itb.misses 0 #
DTB misses
@@ -169,31 +170,31 @@
system.cpu.itb.write_hits 0 #
DTB write hits
system.cpu.itb.write_misses 0 #
DTB write misses
system.cpu.l2cache.ReadExReq_accesses 51 #
number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52500
# average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52264.705882
# average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40098.039216
# average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 2677500 #
number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency 2665500 #
number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 #
miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 51 #
number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2045000
# number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1
# mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 51 #
number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 390 #
number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52052.835052
# average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40023.195876
# average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency 52091.494845
# average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40048.969072
# average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 2 #
number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 20196500 #
number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency 20211500 #
number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.994872 #
miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 388 #
number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 15529000
# number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency 15539000
# number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994872 #
mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 388 #
number of ReadReq MSHR misses
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