changeset b6482c4c89e3 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=b6482c4c89e3
description:
Power ISA: Add an alignment fault to Power ISA and check alignment in
TLB.
diffstat:
3 files changed, 48 insertions(+), 2 deletions(-)
src/arch/power/faults.hh | 16 ++++++++++++++++
src/arch/power/tlb.cc | 32 ++++++++++++++++++++++++++++++--
src/arch/power/tlb.hh | 2 ++
diffs (88 lines):
diff -r 12cfde8f819b -r b6482c4c89e3 src/arch/power/faults.hh
--- a/src/arch/power/faults.hh Wed Feb 10 16:40:54 2010 -0800
+++ b/src/arch/power/faults.hh Fri Feb 12 19:53:19 2010 +0000
@@ -76,6 +76,22 @@
};
+class AlignmentFault : public PowerFault
+{
+ public:
+ AlignmentFault()
+ : PowerFault("Alignment")
+ {
+ }
+
+ bool
+ isAlignmentFault() const
+ {
+ return true;
+ }
+};
+
+
static inline Fault
genMachineCheckFault()
{
diff -r 12cfde8f819b -r b6482c4c89e3 src/arch/power/tlb.cc
--- a/src/arch/power/tlb.cc Wed Feb 10 16:40:54 2010 -0800
+++ b/src/arch/power/tlb.cc Fri Feb 12 19:53:19 2010 +0000
@@ -281,9 +281,27 @@
}
Fault
-TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
+TLB::translateInst(RequestPtr req, ThreadContext *tc)
{
-#if !FULL_SYSTEM
+ // Instruction accesses must be word-aligned
+ if (req->getVaddr() & 0x3) {
+ DPRINTF(TLB, "Alignment Fault on %#x, size = %d\n", req->getVaddr(),
+ req->getSize());
+ return new AlignmentFault();
+ }
+
+ Process * p = tc->getProcessPtr();
+
+ Fault fault = p->pTable->translate(req);
+ if (fault != NoFault)
+ return fault;
+
+ return NoFault;
+}
+
+Fault
+TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
+{
Process * p = tc->getProcessPtr();
Fault fault = p->pTable->translate(req);
@@ -291,6 +309,16 @@
return fault;
return NoFault;
+}
+
+Fault
+TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
+{
+#if !FULL_SYSTEM
+ if (mode == Execute)
+ return translateInst(req, tc);
+ else
+ return translateData(req, tc, mode == Write);
#else
fatal("translate atomic not yet implemented\n");
#endif
diff -r 12cfde8f819b -r b6482c4c89e3 src/arch/power/tlb.hh
--- a/src/arch/power/tlb.hh Wed Feb 10 16:40:54 2010 -0800
+++ b/src/arch/power/tlb.hh Fri Feb 12 19:53:19 2010 +0000
@@ -156,6 +156,8 @@
// static helper functions... really
static bool validVirtualAddress(Addr vaddr);
static Fault checkCacheability(RequestPtr &req);
+ Fault translateInst(RequestPtr req, ThreadContext *tc);
+ Fault translateData(RequestPtr req, ThreadContext *tc, bool write);
Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
void translateTiming(RequestPtr req, ThreadContext *tc,
Translation *translation, Mode mode);
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