changeset 9ec11ecd228a in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=9ec11ecd228a
description:
stats: update stats for the changes I pushed re: shared cache occupancy
diffstat:
237 files changed, 5572 insertions(+), 3115 deletions(-)
tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
| 8
tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
| 8
tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
| 16
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
| 2
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout
| 8
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
| 8
tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
| 8
tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout
| 8
tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
| 16
tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
| 8
tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
| 8
tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
| 16
tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini
| 2
tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout
| 8
tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
| 8
tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
| 8
tests/long/00.gzip/ref/sparc/linux/simple-timing/simout
| 8
tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt
| 16
tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini
| 2
tests/long/00.gzip/ref/x86/linux/simple-atomic/simout
| 8
tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt
| 8
tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini
| 5
tests/long/00.gzip/ref/x86/linux/simple-timing/simout
| 8
tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
| 16
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
| 24
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
| 10
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
| 621 ++++-
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
| 20
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
| 10
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
| 394 ++-
tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini
| 4
tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout
| 8
tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
| 8
tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
| 10
tests/long/10.mcf/ref/sparc/linux/simple-timing/simout
| 8
tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt
| 16
tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini
| 6
tests/long/10.mcf/ref/x86/linux/simple-atomic/simout
| 10
tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt
| 8
tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini
| 7
tests/long/10.mcf/ref/x86/linux/simple-timing/simout
| 8
tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
| 16
tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini
| 4
tests/long/20.parser/ref/x86/linux/simple-atomic/simout
| 8
tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt
| 8
tests/long/20.parser/ref/x86/linux/simple-timing/config.ini
| 7
tests/long/20.parser/ref/x86/linux/simple-timing/simout
| 8
tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
| 16
tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
| 10
tests/long/30.eon/ref/alpha/tru64/o3-timing/simout
| 10
tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt
| 16
tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini
| 2
tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout
| 8
tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
| 8
tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
| 8
tests/long/30.eon/ref/alpha/tru64/simple-timing/simout
| 8
tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt
| 16
tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
| 8
tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simerr
| 2
tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout
| 8
tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
| 16
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
| 2
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr
| 2
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
| 8
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
| 8
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
| 10
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simerr
| 2
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout
| 10
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
| 16
tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
| 8
tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
| 8
tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
| 16
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
| 2
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout
| 8
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
| 8
tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
| 8
tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout
| 8
tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
| 16
tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini
| 2
tests/long/50.vortex/ref/sparc/linux/simple-atomic/simerr
| 1122 +++++-----
tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout
| 8
tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
| 8
tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
| 8
tests/long/50.vortex/ref/sparc/linux/simple-timing/simerr
| 1122 +++++-----
tests/long/50.vortex/ref/sparc/linux/simple-timing/simout
| 8
tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt
| 16
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
| 8
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout
| 8
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
| 18
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
| 2
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout
| 8
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
| 8
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
| 8
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout
| 8
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
| 16
tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini
| 2
tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout
| 8
tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
| 8
tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini
| 5
tests/long/60.bzip2/ref/x86/linux/simple-timing/simout
| 8
tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt
| 16
tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
| 8
tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout
| 10
tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
| 16
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
| 2
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout
| 8
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
| 8
tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
| 8
tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout
| 8
tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
| 16
tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini
| 2
tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout
| 8
tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
| 8
tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
| 8
tests/long/70.twolf/ref/sparc/linux/simple-timing/simout
| 8
tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt
| 16
tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini
| 4
tests/long/70.twolf/ref/x86/linux/simple-atomic/simout
| 10
tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt
| 8
tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini
| 5
tests/long/70.twolf/ref/x86/linux/simple-timing/simout
| 8
tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt
| 16
tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
| 14
tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
| 8
tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
| 8
tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini
| 5
tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout
| 8
tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt
| 14
tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
| 8
tests/quick/00.hello/ref/alpha/linux/o3-timing/simout
| 10
tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt
| 14
tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini
| 2
tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout
| 8
tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt
| 8
tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
| 8
tests/quick/00.hello/ref/alpha/linux/simple-timing/simout
| 8
tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt
| 14
tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
| 8
tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr
| 2
tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout
| 8
tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt
| 14
tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
| 2
tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr
| 2
tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout
| 8
tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
| 8
tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
| 8
tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr
| 2
tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout
| 8
tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt
| 14
tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini
| 2
tests/quick/00.hello/ref/arm/linux/simple-atomic/simout
| 8
tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt
| 8
tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini
| 5
tests/quick/00.hello/ref/mips/linux/inorder-timing/simout
| 8
tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt
| 14
tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini
| 5
tests/quick/00.hello/ref/mips/linux/o3-timing/simout
| 10
tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt
| 14
tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
| 2
tests/quick/00.hello/ref/mips/linux/simple-atomic/simout
| 10
tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt
| 6
tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
| 5
tests/quick/00.hello/ref/mips/linux/simple-timing/simout
| 10
tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt
| 14
tests/quick/00.hello/ref/power/linux/o3-timing/config.ini
| 5
tests/quick/00.hello/ref/power/linux/o3-timing/simerr
| 2
tests/quick/00.hello/ref/power/linux/o3-timing/simout
| 8
tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt
| 14
tests/quick/00.hello/ref/power/linux/simple-atomic/config.ini
| 2
tests/quick/00.hello/ref/power/linux/simple-atomic/simerr
| 2
tests/quick/00.hello/ref/power/linux/simple-atomic/simout
| 8
tests/quick/00.hello/ref/power/linux/simple-atomic/stats.txt
| 6
tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini
| 2
tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout
| 8
tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt
| 8
tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
| 8
tests/quick/00.hello/ref/sparc/linux/simple-timing/simout
| 8
tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt
| 14
tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini
| 2
tests/quick/00.hello/ref/x86/linux/simple-atomic/simout
| 8
tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt
| 8
tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini
| 8
tests/quick/00.hello/ref/x86/linux/simple-timing/simout
| 8
tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt
| 14
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
| 12
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
| 8
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
| 230 --
tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini
| 8
tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout
| 8
tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt
| 14
tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini
| 2
tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout
| 8
tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
| 8
tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini
| 8
tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout
| 8
tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt
| 14
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
| 24
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
| 10
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
| 493 +++-
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
| 20
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
| 10
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
| 314 +-
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
| 24
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
| 10
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
| 619 ++++-
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
| 20
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
| 10
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
| 394 ++-
tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
| 2
tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout
| 8
tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
| 6
tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
| 8
tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout
| 8
tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
| 14
tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
| 26
tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
| 4
tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
| 8
tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
| 172 +
tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
| 26
tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
| 4
tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
| 8
tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
| 208 +
tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
| 20
tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
| 8
tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
| 210 +
tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
| 20
tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
| 8
tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
| 172 +
tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
| 20
tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
| 8
tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
| 208 +
tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini
| 18
tests/quick/50.memtest/ref/alpha/linux/memtest/simout
| 8
tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt
| 342 ++-
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
| 28
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
| 12
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
| 22
diffs (truncated from 16322 to 300 lines):
diff -r 7732bca47f60 -r 9ec11ecd228a
tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini Wed Feb 24
13:46:55 2010 -0800
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini Thu Feb 25
10:08:41 2010 -0800
@@ -109,7 +109,7 @@
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
@@ -281,7 +281,7 @@
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
@@ -316,7 +316,7 @@
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
@@ -358,7 +358,7 @@
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/gzip
gid=100
input=cin
max_stack_size=67108864
diff -r 7732bca47f60 -r 9ec11ecd228a
tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout Wed Feb 24
13:46:55 2010 -0800
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout Thu Feb 25
10:08:41 2010 -0800
@@ -5,10 +5,10 @@
All Rights Reserved
-M5 compiled Jul 6 2009 11:03:45
-M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
-M5 started Jul 6 2009 11:50:56
-M5 executing on maize
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:02:05
+M5 executing on SC2B0619
command line: build/ALPHA_SE/m5.fast -d
build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py
build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff -r 7732bca47f60 -r 9ec11ecd228a
tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt Wed Feb 24
13:46:55 2010 -0800
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt Thu Feb 25
10:08:41 2010 -0800
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 305062 #
Simulator instruction rate (inst/s)
-host_mem_usage 190836 #
Number of bytes of host memory used
-host_seconds 1853.89 #
Real time elapsed on the host
-host_tick_rate 90122857 #
Simulator tick rate (ticks/s)
+host_inst_rate 207071 #
Simulator instruction rate (inst/s)
+host_mem_usage 192708 #
Number of bytes of host memory used
+host_seconds 2731.20 #
Real time elapsed on the host
+host_tick_rate 61173967 #
Simulator tick rate (ticks/s)
sim_freq 1000000000000 #
Frequency of simulated ticks
sim_insts 565552443 #
Number of instructions simulated
sim_seconds 0.167078 #
Number of seconds simulated
@@ -95,6 +95,8 @@
system.cpu.dcache.fast_writes 0 #
number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 #
number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 #
Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.999561 #
Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 4094.203417 #
Average occupied blocks per context
system.cpu.dcache.overall_accesses 152598107 #
number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 29275.574871
# average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 24763.765109
# average overall mshr miss latency
@@ -201,6 +203,8 @@
system.cpu.icache.fast_writes 0 #
number of fast writes performed
system.cpu.icache.mshr_cap_events 0 #
number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 #
Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.375881 #
Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 769.803945 #
Average occupied blocks per context
system.cpu.icache.overall_accesses 66014406 #
number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 36214.713430
# average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 35498.337029
# average overall mshr miss latency
@@ -391,6 +395,10 @@
system.cpu.l2cache.fast_writes 0 #
number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 #
number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 #
Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0 0.051040 #
Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.447409 #
Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 1672.465668 #
Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 14660.696789 #
Average occupied blocks per context
system.cpu.l2cache.overall_accesses 473826 #
number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34265.684253
# average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31126.127143
# average overall mshr miss latency
diff -r 7732bca47f60 -r 9ec11ecd228a
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini Wed Feb
24 13:46:55 2010 -0800
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini Thu Feb
25 10:08:41 2010 -0800
@@ -57,7 +57,7 @@
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/gzip
gid=100
input=cin
max_stack_size=67108864
diff -r 7732bca47f60 -r 9ec11ecd228a
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout Wed Feb 24
13:46:55 2010 -0800
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout Thu Feb 25
10:08:41 2010 -0800
@@ -5,10 +5,10 @@
All Rights Reserved
-M5 compiled Apr 21 2009 16:38:39
-M5 revision e6dd09514462 6117 default qtip tip stats-update
-M5 started Apr 21 2009 16:39:08
-M5 executing on zizzer
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 02:36:02
+M5 executing on SC2B0619
command line: build/ALPHA_SE/m5.fast -d
build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic -re
tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff -r 7732bca47f60 -r 9ec11ecd228a
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt Wed Feb
24 13:46:55 2010 -0800
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt Thu Feb
25 10:08:41 2010 -0800
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 3845310 #
Simulator instruction rate (inst/s)
-host_mem_usage 195720 #
Number of bytes of host memory used
-host_seconds 156.52 #
Real time elapsed on the host
-host_tick_rate 1922667398 #
Simulator tick rate (ticks/s)
+host_inst_rate 1810362 #
Simulator instruction rate (inst/s)
+host_mem_usage 184036 #
Number of bytes of host memory used
+host_seconds 332.45 #
Real time elapsed on the host
+host_tick_rate 905187706 #
Simulator tick rate (ticks/s)
sim_freq 1000000000000 #
Frequency of simulated ticks
sim_insts 601856964 #
Number of instructions simulated
sim_seconds 0.300931 #
Number of seconds simulated
diff -r 7732bca47f60 -r 9ec11ecd228a
tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini Wed Feb
24 13:46:55 2010 -0800
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini Thu Feb
25 10:08:41 2010 -0800
@@ -45,7 +45,7 @@
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
@@ -80,7 +80,7 @@
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
@@ -115,7 +115,7 @@
latency=10000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
@@ -157,7 +157,7 @@
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/gzip
gid=100
input=cin
max_stack_size=67108864
diff -r 7732bca47f60 -r 9ec11ecd228a
tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout Wed Feb 24
13:46:55 2010 -0800
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout Thu Feb 25
10:08:41 2010 -0800
@@ -5,10 +5,10 @@
All Rights Reserved
-M5 compiled Apr 22 2009 06:58:26
-M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff
-M5 started Apr 22 2009 07:05:42
-M5 executing on maize
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 02:27:06
+M5 executing on SC2B0619
command line: build/ALPHA_SE/m5.fast -d
build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re
tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff -r 7732bca47f60 -r 9ec11ecd228a
tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt Wed Feb
24 13:46:55 2010 -0800
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt Thu Feb
25 10:08:41 2010 -0800
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 2876228 #
Simulator instruction rate (inst/s)
-host_mem_usage 205052 #
Number of bytes of host memory used
-host_seconds 209.25 #
Real time elapsed on the host
-host_tick_rate 3718015194 #
Simulator tick rate (ticks/s)
+host_inst_rate 1555765 #
Simulator instruction rate (inst/s)
+host_mem_usage 191800 #
Number of bytes of host memory used
+host_seconds 386.86 #
Real time elapsed on the host
+host_tick_rate 2011092592 #
Simulator tick rate (ticks/s)
sim_freq 1000000000000 #
Frequency of simulated ticks
sim_insts 601856964 #
Number of instructions simulated
sim_seconds 0.778004 #
Number of seconds simulated
@@ -50,6 +50,8 @@
system.cpu.dcache.fast_writes 0 #
number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 #
number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 #
Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.999559 #
Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 4094.195523 #
Average occupied blocks per context
system.cpu.dcache.overall_accesses 153965363 #
number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 42750.401322
# average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 39750.401322
# average overall mshr miss latency
@@ -119,6 +121,8 @@
system.cpu.icache.fast_writes 0 #
number of fast writes performed
system.cpu.icache.mshr_cap_events 0 #
number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 #
Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.328723 #
Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 673.225223 #
Average occupied blocks per context
system.cpu.icache.overall_accesses 601861898 #
number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 56000
# average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 53000
# average overall mshr miss latency
@@ -209,6 +213,10 @@
system.cpu.l2cache.fast_writes 0 #
number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 #
number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 #
Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0 0.050771 #
Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.447994 #
Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 1663.663316 #
Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 14679.879055 #
Average occupied blocks per context
system.cpu.l2cache.overall_accesses 456190 #
number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000
# average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000
# average overall mshr miss latency
diff -r 7732bca47f60 -r 9ec11ecd228a
tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini Wed Feb 24
13:46:55 2010 -0800
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini Thu Feb 25
10:08:41 2010 -0800
@@ -109,7 +109,7 @@
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
@@ -281,7 +281,7 @@
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
@@ -316,7 +316,7 @@
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
@@ -358,7 +358,7 @@
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/sparc/linux/gzip
gid=100
input=cin
max_stack_size=67108864
diff -r 7732bca47f60 -r 9ec11ecd228a
tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout Wed Feb 24
13:46:55 2010 -0800
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout Thu Feb 25
10:08:41 2010 -0800
@@ -5,10 +5,10 @@
All Rights Reserved
-M5 compiled Jul 6 2009 11:07:18
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev
