# HG changeset patch
# User Brad Beckmann <[email protected]>
# Date 1268941825 25200
# Node ID c2db9da78da715a22d76e92e0cabbced82dcef9f
# Parent d657b9a0875113dbb453986391661fb3c7fa669c
m5: Fixed request read bug flagged by Valgrind
Previously the recording of an uncached read occurred after the request was
possibly deleted within the translateTiming function.
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -432,6 +432,10 @@
Addr split_addr = roundDown(addr + data_size - 1, block_size);
assert(split_addr <= addr || split_addr - addr < block_size);
+ // This will need a new way to tell if it's hooked up to a cache or not.
+ if (req->isUncacheable())
+ recordEvent("Uncached Write");
+
_status = DTBWaitResponse;
if (split_addr > addr) {
RequestPtr req1, req2;
@@ -461,10 +465,6 @@
traceData->setAddr(addr);
}
- // This will need a new way to tell if it has a dcache attached.
- if (req->isUncacheable())
- recordEvent("Uncached Read");
-
return NoFault;
}
@@ -510,7 +510,6 @@
return read(addr, *(uint32_t*)&data, flags);
}
-
template<>
Fault
TimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
@@ -555,6 +554,10 @@
Addr split_addr = roundDown(addr + data_size - 1, block_size);
assert(split_addr <= addr || split_addr - addr < block_size);
+ // This will need a new way to tell if it's hooked up to a cache or not.
+ if (req->isUncacheable())
+ recordEvent("Uncached Write");
+
T *dataP = new T;
*dataP = TheISA::htog(data);
_status = DTBWaitResponse;
@@ -586,10 +589,6 @@
traceData->setData(data);
}
- // This will need a new way to tell if it's hooked up to a cache or not.
- if (req->isUncacheable())
- recordEvent("Uncached Write");
-
// If the write needs to have a fault on the access, consider calling
// changeStatus() and changing it to "bad addr write" or something.
return NoFault;
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev
