This patch is OK, but it reminds me that it would be nice to rename the "version" field to something like "id". It took me a while to figure out that's what "version" really means in Ruby.
On Thu, Mar 18, 2010 at 3:46 PM, Brad Beckmann <[email protected]> wrote: > # HG changeset patch > # User Brad Beckmann <[email protected]> > # Date 1268935352 25200 > # Node ID d657b9a0875113dbb453986391661fb3c7fa669c > # Parent dae220c537fa5ac8a6a5ce5e0d10cb6fc124a0db > ruby: Python config files now sets a unique id for each sequencer > > diff --git a/configs/ruby/MESI_CMP_directory.py > b/configs/ruby/MESI_CMP_directory.py > --- a/configs/ruby/MESI_CMP_directory.py > +++ b/configs/ruby/MESI_CMP_directory.py > @@ -76,7 +76,8 @@ > l1d_cache = L1Cache(size = options.l1d_size, > assoc = options.l1d_assoc) > > - cpu_seq = RubySequencer(icache = l1i_cache, > + cpu_seq = RubySequencer(version = i, > + icache = l1i_cache, > dcache = l1d_cache, > physMemPort = phys_mem.port, > physmem = phys_mem) > diff --git a/configs/ruby/MI_example.py b/configs/ruby/MI_example.py > --- a/configs/ruby/MI_example.py > +++ b/configs/ruby/MI_example.py > @@ -71,7 +71,8 @@ > # > # Only one unified L1 cache exists. Can cache instructions and data. > # > - cpu_seq = RubySequencer(icache = cache, > + cpu_seq = RubySequencer(version = i, > + icache = cache, > dcache = cache, > physMemPort = phys_mem.port, > physmem = phys_mem) > diff --git a/configs/ruby/MOESI_CMP_directory.py > b/configs/ruby/MOESI_CMP_directory.py > --- a/configs/ruby/MOESI_CMP_directory.py > +++ b/configs/ruby/MOESI_CMP_directory.py > @@ -76,7 +76,8 @@ > l1d_cache = L1Cache(size = options.l1d_size, > assoc = options.l1d_assoc) > > - cpu_seq = RubySequencer(icache = l1i_cache, > + cpu_seq = RubySequencer(version = i, > + icache = l1i_cache, > dcache = l1d_cache, > physMemPort = phys_mem.port, > physmem = phys_mem) > diff --git a/configs/ruby/MOESI_CMP_token.py b/configs/ruby/MOESI_CMP_token.py > --- a/configs/ruby/MOESI_CMP_token.py > +++ b/configs/ruby/MOESI_CMP_token.py > @@ -82,7 +82,8 @@ > l1d_cache = L1Cache(size = options.l1d_size, > assoc = options.l1d_assoc) > > - cpu_seq = RubySequencer(icache = l1i_cache, > + cpu_seq = RubySequencer(version = i, > + icache = l1i_cache, > dcache = l1d_cache, > physMemPort = phys_mem.port, > physmem = phys_mem) > diff --git a/configs/ruby/MOESI_hammer.py b/configs/ruby/MOESI_hammer.py > --- a/configs/ruby/MOESI_hammer.py > +++ b/configs/ruby/MOESI_hammer.py > @@ -77,7 +77,8 @@ > l2_cache = L2Cache(size = options.l2_size, > assoc = options.l2_assoc) > > - cpu_seq = RubySequencer(icache = l1i_cache, > + cpu_seq = RubySequencer(version = i, > + icache = l1i_cache, > dcache = l1d_cache, > physMemPort = phys_mem.port, > physmem = phys_mem) > > _______________________________________________ > m5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/m5-dev > _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
