It is actually in the parser, but it appears that the AST wasn't ever built. Certainly be easy to add.
Nate > No, SLICC does not have a logical negation operator. > > Brad > > -----Original Message----- > From: [email protected] [mailto:[email protected]] On Behalf Of > Steve Reinhardt > Sent: Thursday, March 18, 2010 4:15 PM > To: M5 Developer List > Subject: Re: [m5-dev] [PATCH 03 of 31] ruby: Fix MOESI_hammer cache profiler > calls for L2 misses > > Hi Brad, > > Does SLICC have a logical negation operator? You know my opinion > about boolean tests coded as explicit comparisons with true and false > :-). > > Steve > > On Thu, Mar 18, 2010 at 3:46 PM, Brad Beckmann <[email protected]> wrote: >> # HG changeset patch >> # User Brad Beckmann <[email protected]> >> # Date 1268935351 25200 >> # Node ID da1412c026c13c4adbaa86ddeda52835a4388640 >> # Parent 72e11133a96f1b7580a8f75f2594b8dfd0e36372 >> ruby: Fix MOESI_hammer cache profiler calls for L2 misses >> >> diff --git a/src/mem/protocol/MOESI_hammer-cache.sm >> b/src/mem/protocol/MOESI_hammer-cache.sm >> --- a/src/mem/protocol/MOESI_hammer-cache.sm >> +++ b/src/mem/protocol/MOESI_hammer-cache.sm >> @@ -683,7 +683,8 @@ >> L1IcacheMemory.profileMiss(in_msg); >> } else if (L1DcacheMemory.isTagPresent(address)) { >> L1DcacheMemory.profileMiss(in_msg); >> - } else { >> + } >> + if (L2cacheMemory.isTagPresent(address) == false) { >> L2cacheMemory.profileMiss(in_msg); >> } >> } >> @@ -724,12 +725,14 @@ >> transition({I, S, O, M, MM}, L2_to_L1D) { >> ii_allocateL1DCacheBlock; >> tt_copyFromL2toL1; // Not really needed for state I >> + uu_profileMiss; >> rr_deallocateL2CacheBlock; >> } >> >> transition({I, S, O, M, MM}, L2_to_L1I) { >> jj_allocateL1ICacheBlock; >> tt_copyFromL2toL1; // Not really needed for state I >> + uu_profileMiss; >> rr_deallocateL2CacheBlock; >> } >> >> >> _______________________________________________ >> m5-dev mailing list >> [email protected] >> http://m5sim.org/mailman/listinfo/m5-dev >> > _______________________________________________ > m5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/m5-dev > > > _______________________________________________ > m5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/m5-dev > > _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
