# HG changeset patch
# User Brad Beckmann <[email protected]>
# Date 1269019051 25200
# Node ID b290241635cdf5b4937ef13a13a1beab0e4beccd
# Parent 44ed5e0c7228c2355a5b99c004c424abaefb6a3f
m5: Fixed TraceData delete bug when SimpleTimingCPU deletes the trace data, but
the instruction fails to realize that.
diff --git a/src/arch/alpha/isa/mem.isa b/src/arch/alpha/isa/mem.isa
--- a/src/arch/alpha/isa/mem.isa
+++ b/src/arch/alpha/isa/mem.isa
@@ -273,9 +273,12 @@
}
if (fault == NoFault) {
+ bool traceDataDeleted = false;
fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
- memAccessFlags, NULL);
- if (traceData) { traceData->setData(Mem); }
+ memAccessFlags, NULL, &traceDataDeleted);
+ if (traceData && (!traceDataDeleted)) {
+ traceData->setData(Mem);
+ }
}
if (fault == NoFault) {
@@ -308,9 +311,12 @@
}
if (fault == NoFault) {
+ bool traceDataDeleted = false;
fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
- memAccessFlags, &write_result);
- if (traceData) { traceData->setData(Mem); }
+ memAccessFlags, &write_result,
&traceDataDeleted);
+ if (traceData && (!traceDataDeleted)) {
+ traceData->setData(Mem);
+ }
}
if (fault == NoFault) {
@@ -342,9 +348,12 @@
}
if (fault == NoFault) {
+ bool traceDataDeleted = false;
fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
- memAccessFlags, NULL);
- if (traceData) { traceData->setData(Mem); }
+ memAccessFlags, NULL, &traceDataDeleted);
+ if (traceData && (!traceDataDeleted)) {
+ traceData->setData(Mem);
+ }
}
return fault;
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -444,7 +444,8 @@
template <class T>
Fault
-AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
+AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res,
+ bool *traceDataDeleted)
{
// use the CPU's statically allocated write request and packet objects
Request *req = &data_write_req;
@@ -560,6 +561,13 @@
}
}
+template <class T>
+Fault
+AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
+{
+ bool dummy;
+ return write(*(uint64_t*)&data, addr, flags, res, &dummy);
+}
#ifndef DOXYGEN_SHOULD_SKIP_THIS
@@ -593,20 +601,58 @@
AtomicSimpleCPU::write(uint8_t data, Addr addr,
unsigned flags, uint64_t *res);
+template
+Fault
+AtomicSimpleCPU::write(Twin32_t data, Addr addr,
+ unsigned flags, uint64_t *res,
+ bool *traceDataDeleted);
+
+template
+Fault
+AtomicSimpleCPU::write(Twin64_t data, Addr addr,
+ unsigned flags, uint64_t *res,
+ bool *traceDataDeleted);
+
+template
+Fault
+AtomicSimpleCPU::write(uint64_t data, Addr addr,
+ unsigned flags, uint64_t *res,
+ bool *traceDataDeleted);
+
+template
+Fault
+AtomicSimpleCPU::write(uint32_t data, Addr addr,
+ unsigned flags, uint64_t *res,
+ bool *traceDataDeleted);
+
+template
+Fault
+AtomicSimpleCPU::write(uint16_t data, Addr addr,
+ unsigned flags, uint64_t *res,
+ bool *traceDataDeleted);
+
+template
+Fault
+AtomicSimpleCPU::write(uint8_t data, Addr addr,
+ unsigned flags, uint64_t *res,
+ bool *traceDataDeleted);
+
#endif //DOXYGEN_SHOULD_SKIP_THIS
template<>
Fault
AtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
{
- return write(*(uint64_t*)&data, addr, flags, res);
+ bool dummy;
+ return write(*(uint64_t*)&data, addr, flags, res, &dummy);
}
template<>
Fault
AtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
{
- return write(*(uint32_t*)&data, addr, flags, res);
+ bool dummy;
+ return write(*(uint32_t*)&data, addr, flags, res, &dummy);
}
@@ -614,9 +660,34 @@
Fault
AtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
{
- return write((uint32_t)data, addr, flags, res);
+ bool dummy;
+ return write((uint32_t)data, addr, flags, res, &dummy);
}
+template<>
+Fault
+AtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res,
+ bool *traceDataDeleted)
+{
+ return write(*(uint64_t*)&data, addr, flags, res, traceDataDeleted);
+}
+
+template<>
+Fault
+AtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res,
+ bool *traceDataDeleted)
+{
+ return write(*(uint32_t*)&data, addr, flags, res, traceDataDeleted);
+}
+
+
+template<>
+Fault
+AtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res,
+ bool *traceDataDeleted)
+{
+ return write((uint32_t)data, addr, flags, res, traceDataDeleted);
+}
void
AtomicSimpleCPU::tick()
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -137,6 +137,10 @@
template <class T>
Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
+ template <class T>
+ Fault write(T data, Addr addr, unsigned flags, uint64_t *res,
+ bool *traceDataDeleted);
+
/**
* Print state of address in memory system via PrintReq (for
* debugging).
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -540,7 +540,8 @@
template <class T>
Fault
-TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
+TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res,
+ bool *traceDataDeleted)
{
const int asid = 0;
const ThreadID tid = 0;
@@ -584,6 +585,8 @@
if (traceData) {
traceData->setAddr(req->getVaddr());
traceData->setData(data);
+ } else {
+ *traceDataDeleted = true;
}
// This will need a new way to tell if it's hooked up to a cache or not.
@@ -595,11 +598,48 @@
return NoFault;
}
+template <class T>
+Fault
+TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
+{
+ bool dummy;
+ return write(data, addr, flags, res, &dummy);
+}
#ifndef DOXYGEN_SHOULD_SKIP_THIS
template
Fault
TimingSimpleCPU::write(Twin32_t data, Addr addr,
+ unsigned flags, uint64_t *res, bool *traceDataDeleted);
+
+template
+Fault
+TimingSimpleCPU::write(Twin64_t data, Addr addr,
+ unsigned flags, uint64_t *res, bool *traceDataDeleted);
+
+template
+Fault
+TimingSimpleCPU::write(uint64_t data, Addr addr,
+ unsigned flags, uint64_t *res, bool *traceDataDeleted);
+
+template
+Fault
+TimingSimpleCPU::write(uint32_t data, Addr addr,
+ unsigned flags, uint64_t *res, bool *traceDataDeleted);
+
+template
+Fault
+TimingSimpleCPU::write(uint16_t data, Addr addr,
+ unsigned flags, uint64_t *res, bool *traceDataDeleted);
+
+template
+Fault
+TimingSimpleCPU::write(uint8_t data, Addr addr,
+ unsigned flags, uint64_t *res, bool *traceDataDeleted);
+
+template
+Fault
+TimingSimpleCPU::write(Twin32_t data, Addr addr,
unsigned flags, uint64_t *res);
template
@@ -631,16 +671,43 @@
template<>
Fault
+TimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res,
+ bool *traceDataDeleted)
+{
+ return write(*(uint64_t*)&data, addr, flags, res, traceDataDeleted);
+}
+
+template<>
+Fault
+TimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res,
+ bool *traceDataDeleted)
+{
+ return write(*(uint32_t*)&data, addr, flags, res, traceDataDeleted);
+}
+
+
+template<>
+Fault
+TimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res,
+ bool *traceDataDeleted)
+{
+ return write((uint32_t)data, addr, flags, res, traceDataDeleted);
+}
+
+template<>
+Fault
TimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
{
- return write(*(uint64_t*)&data, addr, flags, res);
+ bool dummy;
+ return write(*(uint64_t*)&data, addr, flags, res, &dummy);
}
template<>
Fault
TimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
{
- return write(*(uint32_t*)&data, addr, flags, res);
+ bool dummy;
+ return write(*(uint32_t*)&data, addr, flags, res, &dummy);
}
@@ -648,10 +715,10 @@
Fault
TimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
{
- return write((uint32_t)data, addr, flags, res);
+ bool dummy;
+ return write((uint32_t)data, addr, flags, res, &dummy);
}
-
void
TimingSimpleCPU::finishTranslation(WholeTranslationState *state)
{
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -254,6 +254,10 @@
template <class T>
Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
+ template <class T>
+ Fault write(T data, Addr addr, unsigned flags, uint64_t *res,
+ bool *traceDataDeleted);
+
void fetch();
void sendFetch(Fault fault, RequestPtr req, ThreadContext *tc);
void completeIfetch(PacketPtr );
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