changeset 7827a86b8d24 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=7827a86b8d24
description:
ruby: Removed the no longer used rubymem files
diffstat:
3 files changed, 710 deletions(-)
src/mem/RubyMemory.py | 48 ----
src/mem/rubymem.cc | 489 -------------------------------------------------
src/mem/rubymem.hh | 173 -----------------
diffs (truncated from 722 to 300 lines):
diff -r 0ef205fb6d6f -r 7827a86b8d24 src/mem/RubyMemory.py
--- a/src/mem/RubyMemory.py Sun Mar 21 21:22:20 2010 -0700
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,48 +0,0 @@
-# Copyright (c) 2005-2008 The Regents of The University of Michigan
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Nathan Binkert
-
-from m5.params import *
-from m5.proxy import *
-
-from PhysicalMemory import PhysicalMemory
-
-class RubyMemory(PhysicalMemory):
- type = 'RubyMemory'
- clock = Param.Clock('1t', "ruby clock speed")
- phase = Param.Latency('0ns', "ruby clock phase")
- config_file = Param.String("path to the Ruby config file")
- stats_file = Param.String("ruby.stats",
- "file to which ruby dumps its stats")
- num_cpus = Param.Int(1, "Number of CPUs connected to the Ruby memory")
- debug = Param.Bool(False, "Use ruby debug")
- debug_file = Param.String("ruby.debug",
- "path to the Ruby debug output file (stdout if blank)")
- num_dmas = Param.Int(0, "Number of DMA ports connected to the Ruby memory")
- dma_port = VectorPort("Ruby_dma_ports")
- pio_port = Port("Ruby_pio_port")
- ports_per_core = Param.Int(2, "Number of per core. Typical two: icache +
dcache")
diff -r 0ef205fb6d6f -r 7827a86b8d24 src/mem/rubymem.cc
--- a/src/mem/rubymem.cc Sun Mar 21 21:22:20 2010 -0700
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,489 +0,0 @@
-/*
- * Copyright (c) 2001-2005 The Regents of The University of Michigan
- * Copyright (c) 2009 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Daniel Sanchez
- * Brad Beckmann
- */
-
-#include <iostream>
-#include <fstream>
-
-#include "arch/isa_traits.hh"
-#include "base/output.hh"
-#include "base/str.hh"
-#include "base/types.hh"
-#include "config/the_isa.hh"
-#include "mem/ruby/common/Debug.hh"
-#include "mem/ruby/libruby.hh"
-#include "mem/ruby/system/RubyPort.hh"
-#include "mem/ruby/system/Sequencer.hh"
-#include "mem/ruby/system/System.hh"
-#include "mem/rubymem.hh"
-#include "sim/eventq.hh"
-#include "sim/sim_exit.hh"
-
-using namespace std;
-using namespace TheISA;
-
-map<int64_t, PacketPtr> RubyMemory::pending_requests;
-
-RubyMemory::RubyMemory(const Params *p)
- : PhysicalMemory(p)
-{
- ruby_clock = p->clock;
- ruby_phase = p->phase;
-
- ports_per_cpu = p->ports_per_core;
-
- DPRINTF(Ruby, "creating Ruby Memory from file %s\n",
- p->config_file.c_str());
-
- ifstream config(p->config_file.c_str());
-
- if (config.good() == false) {
- fatal("Did not successfully open %s.\n", p->config_file.c_str());
- }
-
- vector<RubyObjConf> sys_conf;
- while (!config.eof()) {
- char buffer[65536];
- config.getline(buffer, sizeof(buffer));
- string line = buffer;
- DPRINTF(Ruby, "%s %d\n", line, line.empty());
- if (line.empty())
- continue;
- vector<string> tokens;
- tokenize(tokens, line, ' ');
- assert(tokens.size() >= 2);
- vector<string> argv;
- for (size_t i=2; i<tokens.size(); i++) {
- std::replace(tokens[i].begin(), tokens[i].end(), '%', ' ');
- std::replace(tokens[i].begin(), tokens[i].end(), '#', '\n');
- argv.push_back(tokens[i]);
- }
- sys_conf.push_back(RubyObjConf(tokens[0], tokens[1], argv));
- tokens.clear();
- argv.clear();
- }
-
- RubySystem::create(sys_conf);
-
- //
- // Create the necessary ruby_ports to connect to the sequencers.
- // This code should be fixed when the configuration systems are unified
- // and the ruby configuration text files no longer exist. Also,
- // it would be great to remove the single ruby_hit_callback func with
- // separate pointers to particular ports to rubymem. However, functional
- // access currently prevent the improvement.
- //
- for (int i = 0; i < params()->num_cpus; i++) {
- RubyPort *p = RubySystem::getPort(csprintf("Sequencer_%d", i),
- ruby_hit_callback);
- ruby_ports.push_back(p);
- }
-
- for (int i = 0; i < params()->num_dmas; i++) {
- RubyPort *p = RubySystem::getPort(csprintf("DMASequencer_%d", i),
- ruby_hit_callback);
- ruby_dma_ports.push_back(p);
- }
-
- pio_port = NULL;
-}
-
-void
-RubyMemory::init()
-{
- if (params()->debug) {
- g_debug_ptr->setVerbosityString("high");
- g_debug_ptr->setDebugTime(1);
- if (!params()->debug_file.empty()) {
- g_debug_ptr->setDebugOutputFile(params()->debug_file.c_str());
- }
- }
-
- //You may want to set some other options...
- //g_debug_ptr->setVerbosityString("med");
- //g_debug_ptr->setFilterString("lsNqST");
- //g_debug_ptr->setFilterString("lsNST");
- //g_debug_ptr->setDebugTime(1);
- //g_debug_ptr->setDebugOutputFile("ruby.debug");
-
- g_system_ptr->clearStats();
-
- if (ports.size() == 0) {
- fatal("RubyMemory object %s is unconnected!", name());
- }
-
- for (PortIterator pi = ports.begin(); pi != ports.end(); ++pi) {
- if (*pi)
- (*pi)->sendStatusChange(Port::RangeChange);
- }
-
- for (PortIterator pi = dma_ports.begin(); pi != dma_ports.end(); ++pi) {
- if (*pi)
- (*pi)->sendStatusChange(Port::RangeChange);
- }
-
- if (pio_port != NULL) {
- pio_port->sendStatusChange(Port::RangeChange);
- }
-
- //Print stats at exit
- rubyExitCB = new RubyExitCallback(this);
- registerExitCallback(rubyExitCB);
-
- //Sched RubyEvent, automatically reschedules to advance ruby cycles
- rubyTickEvent = new RubyEvent(this);
- schedule(rubyTickEvent, curTick + ruby_clock + ruby_phase);
-}
-
-//called by rubyTickEvent
-void
-RubyMemory::tick()
-{
- RubyEventQueue *eq = RubySystem::getEventQueue();
- eq->triggerEvents(eq->getTime() + 1);
- schedule(rubyTickEvent, curTick + ruby_clock);
-}
-
-RubyMemory::~RubyMemory()
-{
- delete g_system_ptr;
-}
-
-Port *
-RubyMemory::getPort(const std::string &if_name, int idx)
-{
- DPRINTF(Ruby, "getting port %d %s\n", idx, if_name);
- DPRINTF(Ruby,
- "number of ruby ports %d and dma ports %d\n",
- ruby_ports.size(),
- ruby_dma_ports.size());
-
- //
- // By default, getPort will be passed an idx of -1. Of course this is an
- // invalid ruby port index and must be a modified
- //
- if (idx == -1) {
- idx = 0;
- }
-
- // Accept request for "functional" port for backwards compatibility
- // with places where this function is called from C++. I'd prefer
- // to move all these into Python someday.
- if (if_name == "functional") {
- assert(idx < ruby_ports.size());
- return new Port(csprintf("%s-functional", name()),
- this,
- ruby_ports[idx]);
- }
-
- //
- // if dma port request, allocate the appropriate prot
- //
- if (if_name == "dma_port") {
- assert(idx < ruby_dma_ports.size());
- RubyMemory::Port* dma_port =
- new Port(csprintf("%s-dma_port%d", name(), idx),
- this,
- ruby_dma_ports[idx]);
- dma_ports.push_back(dma_port);
- return dma_port;
- }
-
- //
- // if pio port, ensure that there is only one
- //
- if (if_name == "pio_port") {
- assert(pio_port == NULL);
- pio_port =
- new RubyMemory::Port("ruby_pio_port", this, NULL);
- return pio_port;
- }
-
- if (if_name != "port") {
- panic("RubyMemory::getPort: unknown port %s requested", if_name);
- }
-
- if (idx >= (int)ports.size()) {
- ports.resize(idx+1);
- }
-
- if (ports[idx] != NULL) {
- panic("RubyMemory::getPort: port %d already assigned", idx);
- }
-
- //
- // Currently this code assumes that each cpu has both a
- // icache and dcache port and therefore divides by ports per cpu. This
will
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