changeset 6c91d41dfc12 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=6c91d41dfc12
description:
        ruby: Python config files now sets a unique id for each sequencer

diffstat:

5 files changed, 10 insertions(+), 5 deletions(-)
configs/ruby/MESI_CMP_directory.py  |    3 ++-
configs/ruby/MI_example.py          |    3 ++-
configs/ruby/MOESI_CMP_directory.py |    3 ++-
configs/ruby/MOESI_CMP_token.py     |    3 ++-
configs/ruby/MOESI_hammer.py        |    3 ++-

diffs (65 lines):

diff -r 441317194b08 -r 6c91d41dfc12 configs/ruby/MESI_CMP_directory.py
--- a/configs/ruby/MESI_CMP_directory.py        Sun Mar 21 21:22:20 2010 -0700
+++ b/configs/ruby/MESI_CMP_directory.py        Sun Mar 21 21:22:20 2010 -0700
@@ -76,7 +76,8 @@
         l1d_cache = L1Cache(size = options.l1d_size,
                             assoc = options.l1d_assoc)
 
-        cpu_seq = RubySequencer(icache = l1i_cache,
+        cpu_seq = RubySequencer(version = i,
+                                icache = l1i_cache,
                                 dcache = l1d_cache,
                                 physMemPort = phys_mem.port,
                                 physmem = phys_mem)
diff -r 441317194b08 -r 6c91d41dfc12 configs/ruby/MI_example.py
--- a/configs/ruby/MI_example.py        Sun Mar 21 21:22:20 2010 -0700
+++ b/configs/ruby/MI_example.py        Sun Mar 21 21:22:20 2010 -0700
@@ -71,7 +71,8 @@
         #
         # Only one unified L1 cache exists.  Can cache instructions and data.
         #
-        cpu_seq = RubySequencer(icache = cache,
+        cpu_seq = RubySequencer(version = i,
+                                icache = cache,
                                 dcache = cache,
                                 physMemPort = phys_mem.port,
                                 physmem = phys_mem)
diff -r 441317194b08 -r 6c91d41dfc12 configs/ruby/MOESI_CMP_directory.py
--- a/configs/ruby/MOESI_CMP_directory.py       Sun Mar 21 21:22:20 2010 -0700
+++ b/configs/ruby/MOESI_CMP_directory.py       Sun Mar 21 21:22:20 2010 -0700
@@ -76,7 +76,8 @@
         l1d_cache = L1Cache(size = options.l1d_size,
                             assoc = options.l1d_assoc)
 
-        cpu_seq = RubySequencer(icache = l1i_cache,
+        cpu_seq = RubySequencer(version = i,
+                                icache = l1i_cache,
                                 dcache = l1d_cache,
                                 physMemPort = phys_mem.port,
                                 physmem = phys_mem)
diff -r 441317194b08 -r 6c91d41dfc12 configs/ruby/MOESI_CMP_token.py
--- a/configs/ruby/MOESI_CMP_token.py   Sun Mar 21 21:22:20 2010 -0700
+++ b/configs/ruby/MOESI_CMP_token.py   Sun Mar 21 21:22:20 2010 -0700
@@ -82,7 +82,8 @@
         l1d_cache = L1Cache(size = options.l1d_size,
                             assoc = options.l1d_assoc)
 
-        cpu_seq = RubySequencer(icache = l1i_cache,
+        cpu_seq = RubySequencer(version = i,
+                                icache = l1i_cache,
                                 dcache = l1d_cache,
                                 physMemPort = phys_mem.port,
                                 physmem = phys_mem)
diff -r 441317194b08 -r 6c91d41dfc12 configs/ruby/MOESI_hammer.py
--- a/configs/ruby/MOESI_hammer.py      Sun Mar 21 21:22:20 2010 -0700
+++ b/configs/ruby/MOESI_hammer.py      Sun Mar 21 21:22:20 2010 -0700
@@ -77,7 +77,8 @@
         l2_cache = L2Cache(size = options.l2_size,
                            assoc = options.l2_assoc)
 
-        cpu_seq = RubySequencer(icache = l1i_cache,
+        cpu_seq = RubySequencer(version = i,
+                                icache = l1i_cache,
                                 dcache = l1d_cache,
                                 physMemPort = phys_mem.port,
                                 physmem = phys_mem)
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