changeset 9f938aea1942 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=9f938aea1942
description:
ruby: Reorganized Ruby topology and protocol files
diffstat:
18 files changed, 1050 insertions(+), 954 deletions(-)
configs/common/Options.py | 4
configs/ruby/MESI_CMP_directory.py | 152 -------------------
configs/ruby/MI_example.py | 131 ----------------
configs/ruby/MOESI_CMP_directory.py | 152 -------------------
configs/ruby/MOESI_CMP_token.py | 162 ---------------------
configs/ruby/MOESI_hammer.py | 139 ------------------
configs/ruby/Ruby.py | 35 +---
configs/ruby/networks/MeshDirCorners.py | 118 ---------------
configs/ruby/protocols/MESI_CMP_directory.py | 152 +++++++++++++++++++
configs/ruby/protocols/MI_example.py | 131 ++++++++++++++++
configs/ruby/protocols/MOESI_CMP_directory.py | 152 +++++++++++++++++++
configs/ruby/protocols/MOESI_CMP_token.py | 162 +++++++++++++++++++++
configs/ruby/protocols/MOESI_hammer.py | 139 ++++++++++++++++++
src/mem/ruby/network/Network.py | 73 ---------
src/mem/ruby/network/topologies/Crossbar.py | 40 +++++
src/mem/ruby/network/topologies/Mesh.py | 103 +++++++++++++
src/mem/ruby/network/topologies/MeshDirCorners.py | 122 +++++++++++++++
src/mem/ruby/network/topologies/SConscript | 37 ++++
diffs (truncated from 2106 to 300 lines):
diff -r 3b9335a18b4c -r 9f938aea1942 configs/common/Options.py
--- a/configs/common/Options.py Sun Mar 21 21:22:21 2010 -0700
+++ b/configs/common/Options.py Sun Mar 21 21:22:22 2010 -0700
@@ -37,8 +37,8 @@
parser.add_option("--clock", action="store", type="string", default='1GHz')
parser.add_option("--num-dirs", type="int", default=1)
parser.add_option("--num-l2caches", type="int", default=1)
-parser.add_option("--topology", type="string", default="crossbar",
- help="'crossbar'|'mesh'")
+parser.add_option("--topology", type="string", default="Crossbar",
+ help="check src/mem/ruby/network/topologies for complete
set")
parser.add_option("--mesh-rows", type="int", default=1,
help="the number of rows in the mesh topology")
parser.add_option("--garnet-network", type="string", default=none,
diff -r 3b9335a18b4c -r 9f938aea1942 configs/ruby/MESI_CMP_directory.py
--- a/configs/ruby/MESI_CMP_directory.py Sun Mar 21 21:22:21 2010 -0700
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,152 +0,0 @@
-# Copyright (c) 2006-2007 The Regents of The University of Michigan
-# Copyright (c) 2009 Advanced Micro Devices, Inc.
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Brad Beckmann
-
-import math
-import m5
-from m5.objects import *
-from m5.defines import buildEnv
-from m5.util import addToPath
-
-#
-# Note: the L1 Cache latency is only used by the sequencer on fast path hits
-#
-class L1Cache(RubyCache):
- latency = 3
-
-#
-# Note: the L2 Cache latency is not currently used
-#
-class L2Cache(RubyCache):
- latency = 15
-
-def create_system(options, phys_mem, piobus, dma_devices):
-
- if buildEnv['PROTOCOL'] != 'MESI_CMP_directory':
- panic("This script requires the MESI_CMP_directory protocol to be
built.")
-
- cpu_sequencers = []
-
- #
- # The ruby network creation expects the list of nodes in the system to be
- # consistent with the NetDest list. Therefore the l1 controller nodes
must be
- # listed before the directory nodes and directory nodes before dma nodes,
etc.
- #
- l1_cntrl_nodes = []
- l2_cntrl_nodes = []
- dir_cntrl_nodes = []
- dma_cntrl_nodes = []
-
- #
- # Must create the individual controllers before the network to ensure the
- # controller constructors are called before the network constructor
- #
-
- for i in xrange(options.num_cpus):
- #
- # First create the Ruby objects associated with this cpu
- #
- l1i_cache = L1Cache(size = options.l1i_size,
- assoc = options.l1i_assoc)
- l1d_cache = L1Cache(size = options.l1d_size,
- assoc = options.l1d_assoc)
-
- cpu_seq = RubySequencer(version = i,
- icache = l1i_cache,
- dcache = l1d_cache,
- physMemPort = phys_mem.port,
- physmem = phys_mem)
-
- if piobus != None:
- cpu_seq.pio_port = piobus.port
-
- l1_cntrl = L1Cache_Controller(version = i,
- sequencer = cpu_seq,
- L1IcacheMemory = l1i_cache,
- L1DcacheMemory = l1d_cache,
- l2_select_num_bits = \
- math.log(options.num_l2caches, 2))
- #
- # Add controllers and sequencers to the appropriate lists
- #
- cpu_sequencers.append(cpu_seq)
- l1_cntrl_nodes.append(l1_cntrl)
-
- for i in xrange(options.num_l2caches):
- #
- # First create the Ruby objects associated with this cpu
- #
- l2_cache = L2Cache(size = options.l2_size,
- assoc = options.l2_assoc)
-
- l2_cntrl = L2Cache_Controller(version = i,
- L2cacheMemory = l2_cache)
-
- l2_cntrl_nodes.append(l2_cntrl)
-
- phys_mem_size = long(phys_mem.range.second) - long(phys_mem.range.first) +
1
- mem_module_size = phys_mem_size / options.num_dirs
-
- for i in xrange(options.num_dirs):
- #
- # Create the Ruby objects associated with the directory controller
- #
-
- mem_cntrl = RubyMemoryControl(version = i)
-
- dir_size = MemorySize('0B')
- dir_size.value = mem_module_size
-
- dir_cntrl = Directory_Controller(version = i,
- directory = \
- RubyDirectoryMemory(version = i,
- size = dir_size),
- memBuffer = mem_cntrl)
-
- dir_cntrl_nodes.append(dir_cntrl)
-
- for i, dma_device in enumerate(dma_devices):
- #
- # Create the Ruby objects associated with the dma controller
- #
- dma_seq = DMASequencer(version = i,
- physMemPort = phys_mem.port,
- physmem = phys_mem)
-
- dma_cntrl = DMA_Controller(version = i,
- dma_sequencer = dma_seq)
-
- dma_cntrl.dma_sequencer.port = dma_device.dma
- dma_cntrl_nodes.append(dma_cntrl)
-
- all_cntrls = l1_cntrl_nodes + \
- l2_cntrl_nodes + \
- dir_cntrl_nodes + \
- dma_cntrl_nodes
-
- return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
diff -r 3b9335a18b4c -r 9f938aea1942 configs/ruby/MI_example.py
--- a/configs/ruby/MI_example.py Sun Mar 21 21:22:21 2010 -0700
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,131 +0,0 @@
-# Copyright (c) 2006-2007 The Regents of The University of Michigan
-# Copyright (c) 2009 Advanced Micro Devices, Inc.
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Brad Beckmann
-
-import m5
-from m5.objects import *
-from m5.defines import buildEnv
-from m5.util import addToPath
-
-#
-# Note: the cache latency is only used by the sequencer on fast path hits
-#
-class Cache(RubyCache):
- latency = 3
-
-def create_system(options, phys_mem, piobus, dma_devices):
-
- if buildEnv['PROTOCOL'] != 'MI_example':
- panic("This script requires the MI_example protocol to be built.")
-
- cpu_sequencers = []
-
- #
- # The ruby network creation expects the list of nodes in the system to be
- # consistent with the NetDest list. Therefore the l1 controller nodes
must be
- # listed before the directory nodes and directory nodes before dma nodes,
etc.
- #
- l1_cntrl_nodes = []
- dir_cntrl_nodes = []
- dma_cntrl_nodes = []
-
- #
- # Must create the individual controllers before the network to ensure the
- # controller constructors are called before the network constructor
- #
-
- for i in xrange(options.num_cpus):
- #
- # First create the Ruby objects associated with this cpu
- # Only one cache exists for this protocol, so by default use the L1D
- # config parameters.
- #
- cache = Cache(size = options.l1d_size,
- assoc = options.l1d_assoc)
-
- #
- # Only one unified L1 cache exists. Can cache instructions and data.
- #
- cpu_seq = RubySequencer(version = i,
- icache = cache,
- dcache = cache,
- physMemPort = phys_mem.port,
- physmem = phys_mem)
-
- if piobus != None:
- cpu_seq.pio_port = piobus.port
-
- l1_cntrl = L1Cache_Controller(version = i,
- sequencer = cpu_seq,
- cacheMemory = cache)
- #
- # Add controllers and sequencers to the appropriate lists
- #
- cpu_sequencers.append(cpu_seq)
- l1_cntrl_nodes.append(l1_cntrl)
-
- phys_mem_size = long(phys_mem.range.second) - long(phys_mem.range.first) +
1
- mem_module_size = phys_mem_size / options.num_dirs
-
- for i in xrange(options.num_dirs):
- #
- # Create the Ruby objects associated with the directory controller
- #
-
- mem_cntrl = RubyMemoryControl(version = i)
-
- dir_size = MemorySize('0B')
- dir_size.value = mem_module_size
-
- dir_cntrl = Directory_Controller(version = i,
- directory = \
- RubyDirectoryMemory(version = i,
- size = dir_size,
- use_map = options.use_map,
- map_levels =
options.map_levels),
- memBuffer = mem_cntrl)
-
- dir_cntrl_nodes.append(dir_cntrl)
-
- for i, dma_device in enumerate(dma_devices):
- #
- # Create the Ruby objects associated with the dma controller
- #
- dma_seq = DMASequencer(version = i,
- physMemPort = phys_mem.port,
- physmem = phys_mem)
-
- dma_cntrl = DMA_Controller(version = i,
- dma_sequencer = dma_seq)
-
- dma_cntrl.dma_sequencer.port = dma_device.dma
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