changeset 7739d67ca64f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=7739d67ca64f
description:
inorder: fix address list bug
diffstat:
3 files changed, 14 insertions(+), 13 deletions(-)
src/cpu/inorder/SConscript | 2 +-
src/cpu/inorder/cpu.cc | 2 +-
src/cpu/inorder/resources/cache_unit.cc | 23 ++++++++++++-----------
diffs (88 lines):
diff -r b78b3a9e205f -r 7739d67ca64f src/cpu/inorder/SConscript
--- a/src/cpu/inorder/SConscript Mon Mar 22 11:19:17 2010 -0700
+++ b/src/cpu/inorder/SConscript Mon Mar 22 15:38:28 2010 -0400
@@ -61,7 +61,7 @@
'InOrderMDU', 'InOrderAGEN', 'InOrderFetchSeq', 'InOrderTLB',
'InOrderBPred',
'InOrderDecode', 'InOrderExecute', 'InOrderInstBuffer',
'InOrderUseDef',
'InOrderGraduation', 'InOrderCachePort', 'RegDepMap', 'Resource',
- 'ThreadModel'])
+ 'ThreadModel', 'AddrDep'])
Source('pipeline_traits.cc')
Source('inorder_dyn_inst.cc')
diff -r b78b3a9e205f -r 7739d67ca64f src/cpu/inorder/cpu.cc
--- a/src/cpu/inorder/cpu.cc Mon Mar 22 11:19:17 2010 -0700
+++ b/src/cpu/inorder/cpu.cc Mon Mar 22 15:38:28 2010 -0400
@@ -1335,7 +1335,7 @@
while (!reqRemoveList.empty()) {
ResourceRequest *res_req = reqRemoveList.front();
- DPRINTF(InOrderCPU, "[tid:%i] [sn:%lli]: Removing Request "
+ DPRINTF(Resource, "[tid:%i] [sn:%lli]: Removing Request "
"[stage_num:%i] [res:%s] [slot:%i] [completed:%i].\n",
res_req->inst->threadNumber,
res_req->inst->seqNum,
diff -r b78b3a9e205f -r 7739d67ca64f src/cpu/inorder/resources/cache_unit.cc
--- a/src/cpu/inorder/resources/cache_unit.cc Mon Mar 22 11:19:17 2010 -0700
+++ b/src/cpu/inorder/resources/cache_unit.cc Mon Mar 22 15:38:28 2010 -0400
@@ -188,12 +188,18 @@
addrList[tid].push_back(req_addr);
addrMap[tid][req_addr] = inst->seqNum;
- DPRINTF(InOrderCachePort,
- "[tid:%i]: [sn:%i]: Address %08p added to dependency list\n",
- inst->readTid(), inst->seqNum, req_addr);
+
DPRINTF(AddrDep,
"[tid:%i]: [sn:%i]: Address %08p added to dependency list\n",
inst->readTid(), inst->seqNum, req_addr);
+
+ //@NOTE: 10 is an arbitrarily "high" number here, but to be exact
+ // we would need to know the # of outstanding accesses
+ // a priori. Information like fetch width, stage width,
+ // and the branch resolution stage would be useful for the
+ // icache_port (among other things). For the dcache, the #
+ // of outstanding cache accesses might be sufficient.
+ assert(addrList[tid].size() < 10);
}
void
@@ -203,6 +209,8 @@
Addr mem_addr = inst->getMemAddr();
+ inst->unsetMemAddr();
+
// Erase from Address List
vector<Addr>::iterator vect_it = find(addrList[tid].begin(),
addrList[tid].end(),
mem_addr);
@@ -1106,8 +1114,6 @@
tid, cache_req->inst->readPC());
cache_req->setMemAccCompleted();
}
-
- inst->unsetMemAddr();
}
void
@@ -1225,10 +1231,6 @@
// Mark slot for removal from resource
slot_remove_list.push_back(req_ptr->getSlot());
-
- DPRINTF(InOrderCachePort,
- "[tid:%i] Squashing request from [sn:%i]\n",
- req_ptr->getInst()->readTid(),
req_ptr->getInst()->seqNum);
} else {
DPRINTF(InOrderCachePort,
"[tid:%i] Request from [sn:%i] squashed, but still
pending completion.\n",
@@ -1246,8 +1248,7 @@
req_ptr->getInst()->getMemAddr());
removeAddrDependency(req_ptr->getInst());
- }
-
+ }
}
map_it++;
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