Actually, all of the recordEvent stuff was really old stuff that I created and never fleshed out. The goal was to feed a pipeline visualization tool like ASIM has. We could just delete all of it.
Nate On Tue, Mar 23, 2010 at 8:54 AM, Steve Reinhardt <[email protected]> wrote: > changeset d21d575a6f99 in /z/repo/m5 > details: http://repo.m5sim.org/m5?cmd=changeset;node=d21d575a6f99 > description: > cpu: get rid of uncached access "events" > These recordEvent() calls could cause crashes since they > access the req pointer after it's potentially been > deleted during a failed translation call. (Similar > problem to the traceData bug fixed in the previous cset.) > > Moving them above the translation call (as was done > recentlyi in cset 8b2b8e5e7d35) avoids the crash > but doesn't work, since at that point we don't know if > the access is uncached or not. > > It's not clear why these calls are there, and no one > seems to use them, so we'll just delete them. If they > are needed, they should be moved to somewhere that's > guaranteed to be after the translation completes but > before the request is possibly deleted, e.g., in > finishTranslation(). > > diffstat: > > 2 files changed, 16 deletions(-) > src/cpu/simple/atomic.cc | 8 -------- > src/cpu/simple/timing.cc | 8 -------- > > diffs (50 lines): > > diff -r e21fe6a62b1c -r d21d575a6f99 src/cpu/simple/atomic.cc > --- a/src/cpu/simple/atomic.cc Tue Mar 23 08:50:57 2010 -0700 > +++ b/src/cpu/simple/atomic.cc Tue Mar 23 08:50:59 2010 -0700 > @@ -351,10 +351,6 @@ > } > } > > - // This will need a new way to tell if it has a dcache attached. > - if (req->isUncacheable()) > - recordEvent("Uncached Read"); > - > //If there's a fault, return it > if (fault != NoFault) { > if (req->isPrefetch()) { > @@ -523,10 +519,6 @@ > } > } > > - // This will need a new way to tell if it's hooked up to a cache or > not. > - if (req->isUncacheable()) > - recordEvent("Uncached Write"); > - > //If there's a fault or we don't need to access a second cache line, > //stop now. > if (fault != NoFault || secondAddr <= addr) > diff -r e21fe6a62b1c -r d21d575a6f99 src/cpu/simple/timing.cc > --- a/src/cpu/simple/timing.cc Tue Mar 23 08:50:57 2010 -0700 > +++ b/src/cpu/simple/timing.cc Tue Mar 23 08:50:59 2010 -0700 > @@ -436,10 +436,6 @@ > Addr split_addr = roundDown(addr + data_size - 1, block_size); > assert(split_addr <= addr || split_addr - addr < block_size); > > - // This will need a new way to tell if it's hooked up to a cache or not. > - if (req->isUncacheable()) > - recordEvent("Uncached Write"); > - > _status = DTBWaitResponse; > if (split_addr > addr) { > RequestPtr req1, req2; > @@ -558,10 +554,6 @@ > Addr split_addr = roundDown(addr + data_size - 1, block_size); > assert(split_addr <= addr || split_addr - addr < block_size); > > - // This will need a new way to tell if it's hooked up to a cache or not. > - if (req->isUncacheable()) > - recordEvent("Uncached Write"); > - > T *dataP = new T; > *dataP = TheISA::htog(data); > _status = DTBWaitResponse; > _______________________________________________ > m5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/m5-dev > > _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
