X86 support is enabled for M5, although isn't 100% complete or debugged. There are no x86 checkpoints or ways to generate them currently, but we do have a number of x86 regression tests. Those check the statistics of the simple atomic CPU, so if you were to use them directly you'd need to fake those statistics from your CPU. In SE mode, you can use the statetrace tool in util which uses ptrace and an M5 tracer (nativeTrace, I believe) to compare some register state and the IP instruction by instruction between an actual CPU and M5. You'd need to figure out how to get trace information out of your CPU into the objects the tracer provides.
Gabe Rathijit Sen wrote: > Dear Gabe: > > We are working on integrating the Bochs x86 cpu model with the M5 > framework. We need some testing infrastructure to validate the resulting > system. More specifically we need the following: > > 1) M5 checkpoints for x86 > 2) scripts to create above checkpoints > 3) regression testing framework > > We think that you have been working on enabling x86 support for M5. Can > you share some of your testing infrastructure that we can reuse for the > above work? > > Thanks, > > Rathijit > > Arka > > > > > > _______________________________________________ > m5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/m5-dev > _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
