Woops, sorry. No extra space before the if, just one after it. Also, if you're fascinated by our particular set of rules and want to learn more (or if you're just bored :) ), the actual style guide is here: http://m5sim.org/wiki/index.php/Coding_Style
Gabe Gabe Black wrote: > There are some style issues with this code, although it looks like they > might partially be holdovers from the original code. There should be > spaces before and after the "="s, the "if", the ">=", and after the ")" > and the ","s. "else" should be on the same line as the closing bracket > of the if, and you probably should put the code under it in brackets > since the "if" part is in brackets. > > Gabe > > Maximilien Breughe wrote: > >> # HG changeset patch >> # User Maximilien Breughe <[email protected]> >> # Date 1271144284 -7200 >> # Branch dev-perflab >> # Node ID 401bc1d45798b11db33cf5c995c7c44fceacc4c3 >> # Parent 9342cbe0c2c9fd94300a3762f518f3d4313f2951 >> Bug fix: Another branch predictor fix >> ============================ >> >> Branches can cause squashes for 2 reasons: >> 1) branch prediction >> 2) branch resolution >> >> Prediction happens in the Decode-stage. At this point, no information is >> known about what path is taken. >> Therefore a squash caused at prediction-time should not update the branch >> predictor and hence the bug fix. >> >> Only squashes resulting from the branch resolution (in the Execution-stage) >> can update the branch predictor. >> >> Another possibility was to update the branch predictor only at the >> graduation-stage. >> >> diff -r 9342cbe0c2c9 -r 401bc1d45798 >> src/cpu/inorder/resources/branch_predictor.cc >> --- a/src/cpu/inorder/resources/branch_predictor.cc Fri Mar 26 09:57:52 >> 2010 +0100 >> +++ b/src/cpu/inorder/resources/branch_predictor.cc Tue Apr 13 09:38:04 >> 2010 +0200 >> @@ -142,10 +142,13 @@ >> InstSeqNum squash_seq_num, ThreadID tid) >> { >> DPRINTF(InOrderBPred, "Squashing...\n"); >> - Addr corr_targ=inst->readPredPC(); >> - bool taken=inst->predTaken(); >> - branchPred.squash(squash_seq_num,corr_targ,taken,tid); >> -// branchPred.squash(squash_seq_num,tid); >> + if(squash_stage>=ThePipeline::BackEndStartStage){ >> + Addr corr_targ=inst->readPredPC(); >> + bool taken=inst->predTaken(); >> + branchPred.squash(squash_seq_num,corr_targ,taken,tid); >> + } >> + else >> + branchPred.squash(squash_seq_num,tid); >> } >> >> void >> _______________________________________________ >> m5-dev mailing list >> [email protected] >> http://m5sim.org/mailman/listinfo/m5-dev >> >> > > _______________________________________________ > m5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/m5-dev > _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
