changeset 586b0e3a12b3 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=586b0e3a12b3
description:
        tick: rename Clock namespace to SimClock

diffstat:

20 files changed, 39 insertions(+), 38 deletions(-)
src/arch/alpha/freebsd/system.cc |    2 +-
src/arch/alpha/linux/system.cc   |    2 +-
src/arch/alpha/tru64/process.cc  |    2 +-
src/arch/mips/linux/system.cc    |    2 +-
src/cpu/base.hh                  |    2 +-
src/dev/alpha/tsunami_io.cc      |    2 +-
src/dev/etherdump.cc             |    4 ++--
src/dev/i8254xGBe.cc             |    4 ++--
src/dev/i8254xGBe.hh             |    2 +-
src/dev/intel_8254_timer.cc      |    2 +-
src/dev/mc146818.cc              |    2 +-
src/dev/mc146818.hh              |    2 +-
src/dev/mips/malta_io.cc         |    2 +-
src/dev/uart8250.cc              |    4 ++--
src/mem/tport.cc                 |    2 +-
src/sim/core.cc                  |    6 +++---
src/sim/core.hh                  |    4 ++--
src/sim/pseudo_inst.cc           |   25 +++++++++++++------------
src/sim/stat_control.cc          |    2 +-
src/sim/syscall_emul.hh          |    4 ++--

diffs (truncated from 365 to 300 lines):

diff -r c0ea4df1ddab -r 586b0e3a12b3 src/arch/alpha/freebsd/system.cc
--- a/src/arch/alpha/freebsd/system.cc  Thu Apr 15 16:24:10 2010 -0700
+++ b/src/arch/alpha/freebsd/system.cc  Thu Apr 15 16:24:12 2010 -0700
@@ -77,7 +77,7 @@
     ppc_vaddr = (Addr)tc->readIntReg(17);
     timer_vaddr = (Addr)tc->readIntReg(18);
 
-    virtPort.write(ppc_vaddr, (uint32_t)Clock::Frequency);
+    virtPort.write(ppc_vaddr, (uint32_t)SimClock::Frequency);
     virtPort.write(timer_vaddr, (uint32_t)TIMER_FREQUENCY);
 }
 
diff -r c0ea4df1ddab -r 586b0e3a12b3 src/arch/alpha/linux/system.cc
--- a/src/arch/alpha/linux/system.cc    Thu Apr 15 16:24:10 2010 -0700
+++ b/src/arch/alpha/linux/system.cc    Thu Apr 15 16:24:12 2010 -0700
@@ -86,7 +86,7 @@
      * calculated it by using the PIT, RTC, etc.
      */
     if (kernelSymtab->findAddress("est_cycle_freq", addr))
-        virtPort.write(addr, (uint64_t)(Clock::Frequency /
+        virtPort.write(addr, (uint64_t)(SimClock::Frequency /
                     p->boot_cpu_frequency));
 
 
diff -r c0ea4df1ddab -r 586b0e3a12b3 src/arch/alpha/tru64/process.cc
--- a/src/arch/alpha/tru64/process.cc   Thu Apr 15 16:24:10 2010 -0700
+++ b/src/arch/alpha/tru64/process.cc   Thu Apr 15 16:24:12 2010 -0700
@@ -183,7 +183,7 @@
           TypedBufferArg<Tru64::tbl_sysinfo> elp(bufPtr);
 
           const int clk_hz = one_million;
-          elp->si_user = htog(curTick / (Clock::Frequency / clk_hz));
+          elp->si_user = htog(curTick / (SimClock::Frequency / clk_hz));
           elp->si_nice = htog(0);
           elp->si_sys = htog(0);
           elp->si_idle = htog(0);
diff -r c0ea4df1ddab -r 586b0e3a12b3 src/arch/mips/linux/system.cc
--- a/src/arch/mips/linux/system.cc     Thu Apr 15 16:24:10 2010 -0700
+++ b/src/arch/mips/linux/system.cc     Thu Apr 15 16:24:12 2010 -0700
@@ -85,7 +85,7 @@
      * calculated it by using the PIT, RTC, etc.
      */
     if (kernelSymtab->findAddress("est_cycle_freq", addr))
-        virtPort.write(addr, (uint64_t)(Clock::Frequency /
+        virtPort.write(addr, (uint64_t)(SimClock::Frequency /
                     p->boot_cpu_frequency));
 
     /**
diff -r c0ea4df1ddab -r 586b0e3a12b3 src/cpu/base.hh
--- a/src/cpu/base.hh   Thu Apr 15 16:24:10 2010 -0700
+++ b/src/cpu/base.hh   Thu Apr 15 16:24:12 2010 -0700
@@ -98,7 +98,7 @@
     int cpuId() { return _cpuId; }
 
 //    Tick currentTick;
-    inline Tick frequency() const { return Clock::Frequency / clock; }
+    inline Tick frequency() const { return SimClock::Frequency / clock; }
     inline Tick ticks(int numCycles) const { return clock * numCycles; }
     inline Tick curCycle() const { return curTick / clock; }
     inline Tick tickToCycles(Tick val) const { return val / clock; }
diff -r c0ea4df1ddab -r 586b0e3a12b3 src/dev/alpha/tsunami_io.cc
--- a/src/dev/alpha/tsunami_io.cc       Thu Apr 15 16:24:10 2010 -0700
+++ b/src/dev/alpha/tsunami_io.cc       Thu Apr 15 16:24:12 2010 -0700
@@ -80,7 +80,7 @@
 Tick
 TsunamiIO::frequency() const
 {
-    return Clock::Frequency / params()->frequency;
+    return SimClock::Frequency / params()->frequency;
 }
 
 Tick
diff -r c0ea4df1ddab -r 586b0e3a12b3 src/dev/etherdump.cc
--- a/src/dev/etherdump.cc      Thu Apr 15 16:24:10 2010 -0700
+++ b/src/dev/etherdump.cc      Thu Apr 15 16:24:12 2010 -0700
@@ -94,8 +94,8 @@
 EtherDump::dumpPacket(EthPacketPtr &packet)
 {
     pcap_pkthdr pkthdr;
-    pkthdr.seconds = curTick / Clock::Int::s;
-    pkthdr.microseconds = (curTick / Clock::Int::us) % ULL(1000000);
+    pkthdr.seconds = curTick / SimClock::Int::s;
+    pkthdr.microseconds = (curTick / SimClock::Int::us) % ULL(1000000);
     pkthdr.caplen = std::min(packet->length, maxlen);
     pkthdr.len = packet->length;
     stream->write(reinterpret_cast<char *>(&pkthdr), sizeof(pkthdr));
diff -r c0ea4df1ddab -r 586b0e3a12b3 src/dev/i8254xGBe.cc
--- a/src/dev/i8254xGBe.cc      Thu Apr 15 16:24:10 2010 -0700
+++ b/src/dev/i8254xGBe.cc      Thu Apr 15 16:24:12 2010 -0700
@@ -693,7 +693,7 @@
 
     regs.icr = regs.icr() | t;
 
-    Tick itr_interval = Clock::Int::ns * 256 * regs.itr.interval();
+    Tick itr_interval = SimClock::Int::ns * 256 * regs.itr.interval();
     DPRINTF(EthernetIntr,
             "EINT: postInterrupt() curTick: %d itr: %d interval: %d\n",
             curTick, regs.itr.interval(), itr_interval);
@@ -801,7 +801,7 @@
             DPRINTF(Ethernet,
                     "Possibly scheduling interrupt because of imr write\n");
             if (!interEvent.scheduled()) {
-                Tick t = curTick + Clock::Int::ns * 256 * regs.itr.interval();
+                Tick t = curTick + SimClock::Int::ns * 256 * 
regs.itr.interval();
                 DPRINTF(Ethernet, "Scheduling for %d\n", t);
                 schedule(interEvent, t);
             }
diff -r c0ea4df1ddab -r 586b0e3a12b3 src/dev/i8254xGBe.hh
--- a/src/dev/i8254xGBe.hh      Thu Apr 15 16:24:10 2010 -0700
+++ b/src/dev/i8254xGBe.hh      Thu Apr 15 16:24:12 2010 -0700
@@ -171,7 +171,7 @@
      */
     void cpuClearInt();
 
-    Tick intClock() { return Clock::Int::ns * 1024; }
+    Tick intClock() { return SimClock::Int::ns * 1024; }
 
     /** This function is used to restart the clock so it can handle things like
      * draining and resume in one place. */
diff -r c0ea4df1ddab -r 586b0e3a12b3 src/dev/intel_8254_timer.cc
--- a/src/dev/intel_8254_timer.cc       Thu Apr 15 16:24:10 2010 -0700
+++ b/src/dev/intel_8254_timer.cc       Thu Apr 15 16:24:12 2010 -0700
@@ -255,7 +255,7 @@
 
 Intel8254Timer::Counter::CounterEvent::CounterEvent(Counter* c_ptr)
 {
-    interval = (Tick)(Clock::Float::s / 1193180.0);
+    interval = (Tick)(SimClock::Float::s / 1193180.0);
     counter = c_ptr;
 }
 
diff -r c0ea4df1ddab -r 586b0e3a12b3 src/dev/mc146818.cc
--- a/src/dev/mc146818.cc       Thu Apr 15 16:24:10 2010 -0700
+++ b/src/dev/mc146818.cc       Thu Apr 15 16:24:12 2010 -0700
@@ -271,7 +271,7 @@
 MC146818::RTCTickEvent::process()
 {
     DPRINTF(MC146818, "RTC clock tick\n");
-    parent->schedule(this, curTick + Clock::Int::s);
+    parent->schedule(this, curTick + SimClock::Int::s);
     parent->tickClock();
 }
 
diff -r c0ea4df1ddab -r 586b0e3a12b3 src/dev/mc146818.hh
--- a/src/dev/mc146818.hh       Thu Apr 15 16:24:10 2010 -0700
+++ b/src/dev/mc146818.hh       Thu Apr 15 16:24:12 2010 -0700
@@ -71,7 +71,7 @@
 
         RTCTickEvent(MC146818 * _parent) : parent(_parent)
         {
-            parent->schedule(this, curTick + Clock::Int::s);
+            parent->schedule(this, curTick + SimClock::Int::s);
         }
 
         /** Event process to occur at interrupt*/
diff -r c0ea4df1ddab -r 586b0e3a12b3 src/dev/mips/malta_io.cc
--- a/src/dev/mips/malta_io.cc  Thu Apr 15 16:24:10 2010 -0700
+++ b/src/dev/mips/malta_io.cc  Thu Apr 15 16:24:12 2010 -0700
@@ -80,7 +80,7 @@
 Tick
 MaltaIO::frequency() const
 {
-    return Clock::Frequency / params()->frequency;
+    return SimClock::Frequency / params()->frequency;
 }
 
 Tick
diff -r c0ea4df1ddab -r 586b0e3a12b3 src/dev/uart8250.cc
--- a/src/dev/uart8250.cc       Thu Apr 15 16:24:10 2010 -0700
+++ b/src/dev/uart8250.cc       Thu Apr 15 16:24:12 2010 -0700
@@ -90,7 +90,7 @@
 void
 Uart8250::IntrEvent::scheduleIntr()
 {
-    static const Tick interval = 225 * Clock::Int::ns;
+    static const Tick interval = 225 * SimClock::Int::ns;
     DPRINTF(Uart, "Scheduling IER interrupt for %#x, at cycle %lld\n", intrBit,
             curTick + interval);
     if (!scheduled())
@@ -217,7 +217,7 @@
                 if (UART_IER_THRI & IER)
                 {
                     DPRINTF(Uart, "IER: IER_THRI set, scheduling TX 
intrrupt\n");
-                    if (curTick - lastTxInt > 225 * Clock::Int::ns) {
+                    if (curTick - lastTxInt > 225 * SimClock::Int::ns) {
                         DPRINTF(Uart, "-- Interrupting Immediately... %d,%d\n",
                                 curTick, lastTxInt);
                         txIntrEvent.process();
diff -r c0ea4df1ddab -r 586b0e3a12b3 src/mem/tport.cc
--- a/src/mem/tport.cc  Thu Apr 15 16:24:10 2010 -0700
+++ b/src/mem/tport.cc  Thu Apr 15 16:24:12 2010 -0700
@@ -108,7 +108,7 @@
 SimpleTimingPort::schedSendTiming(PacketPtr pkt, Tick when)
 {
     assert(when > curTick);
-    assert(when < curTick + Clock::Int::ms);
+    assert(when < curTick + SimClock::Int::ms);
 
     // Nothing is on the list: add it and schedule an event
     if (transmitList.empty() || when < transmitList.front().tick) {
diff -r c0ea4df1ddab -r 586b0e3a12b3 src/sim/core.cc
--- a/src/sim/core.cc   Thu Apr 15 16:24:10 2010 -0700
+++ b/src/sim/core.cc   Thu Apr 15 16:24:12 2010 -0700
@@ -40,7 +40,7 @@
 
 Tick curTick = 0;
 
-namespace Clock {
+namespace SimClock {
 /// The simulated frequency of curTick. (In ticks per second)
 Tick Frequency;
 
@@ -65,12 +65,12 @@
 Tick ps;
 /* namespace Float */ }
 
-/* namespace Clock */ }
+/* namespace SimClock */ }
 
 void
 setClockFrequency(Tick ticksPerSecond)
 {
-    using namespace Clock;
+    using namespace SimClock;
     Frequency = ticksPerSecond;
     Float::s = static_cast<double>(Frequency);
     Float::ms = Float::s / 1.0e3;
diff -r c0ea4df1ddab -r 586b0e3a12b3 src/sim/core.hh
--- a/src/sim/core.hh   Thu Apr 15 16:24:10 2010 -0700
+++ b/src/sim/core.hh   Thu Apr 15 16:24:12 2010 -0700
@@ -40,7 +40,7 @@
 extern Tick curTick;
 const Tick retryTime = 1000;
 
-namespace Clock {
+namespace SimClock {
 /// The simulated frequency of curTick.
 extern Tick Frequency;
 
@@ -64,7 +64,7 @@
 extern Tick ns;
 extern Tick ps;
 /* namespace Int */ }
-/* namespace Clock */ }
+/* namespace SimClock */ }
 
 void setClockFrequency(Tick ticksPerSecond);
 
diff -r c0ea4df1ddab -r 586b0e3a12b3 src/sim/pseudo_inst.cc
--- a/src/sim/pseudo_inst.cc    Thu Apr 15 16:24:10 2010 -0700
+++ b/src/sim/pseudo_inst.cc    Thu Apr 15 16:24:12 2010 -0700
@@ -93,7 +93,7 @@
 
     EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent();
 
-    Tick resume = curTick + Clock::Int::ns * ns;
+    Tick resume = curTick + SimClock::Int::ns * ns;
 
     mainEventQueue.reschedule(quiesceEvent, resume, true);
 
@@ -128,7 +128,8 @@
 uint64_t
 quiesceTime(ThreadContext *tc)
 {
-    return (tc->readLastActivate() - tc->readLastSuspend()) / Clock::Int::ns;
+    return (tc->readLastActivate() - tc->readLastSuspend()) /
+        SimClock::Int::ns;
 }
 
 #endif
@@ -136,7 +137,7 @@
 uint64_t
 rpns(ThreadContext *tc)
 {
-    return curTick / Clock::Int::ns;
+    return curTick / SimClock::Int::ns;
 }
 
 void
@@ -151,7 +152,7 @@
 void
 m5exit(ThreadContext *tc, Tick delay)
 {
-    Tick when = curTick + delay * Clock::Int::ns;
+    Tick when = curTick + delay * SimClock::Int::ns;
     Event *event = new SimLoopExitEvent("m5_exit instruction encountered", 0);
     mainEventQueue.schedule(event, when);
 }
@@ -229,8 +230,8 @@
         return;
 
 
-    Tick when = curTick + delay * Clock::Int::ns;
-    Tick repeat = period * Clock::Int::ns;
+    Tick when = curTick + delay * SimClock::Int::ns;
+    Tick repeat = period * SimClock::Int::ns;
 
     Stats::StatEvent(false, true, when, repeat);
 }
@@ -242,8 +243,8 @@
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev

Reply via email to