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User who did this: - Gabe Black (gblack) Attached to Project - M5 Bugs Summary - Improve handling of the FSR in SPARC. Task Type - Minor Enhancement Category - ISA Support Status - Assigned Assigned To - Gabe Black Operating System - All Severity - Low Priority - Normal Reported Version - 2.0beta5 Due in Version - Due Date - Undecided Details - SPARC's FSR controls floating point operations and also tracks floating point condition codes. The register should probably be split into a control register and an integer register for the condition codes. That way the condition codes would be renameable like the integer ones, and instructions that set them won't be serializing. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/327 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev