All of the /* issues have been addressed. Ali
On Tue, 01 Jun 2010 18:31:07 -0000, "Nathan Binkert" <[email protected]> wrote: > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/20/#review31 > ----------------------------------------------------------- > > > My comments are very superficial, but I would appreciate the copyright > fixes to make life easier if we ever have to do some copyright nonsense > again (I sure hope not). I have one other minor request. Get rid of lines >> 80 columns for at least the ARM stuff. > > > configs/common/cpu2000.py > <http://reviews.m5sim.org/r/20/#comment143> > > No big deal, but python doesn't require parens for stuff like this. > > > > src/arch/arm/SConscript > <http://reviews.m5sim.org/r/20/#comment144> > > Unless you know that none of this was written by FSU, you probably > shouldn't remove the copyright. > > > > src/arch/arm/faults.hh > <http://reviews.m5sim.org/r/20/#comment145> > > You're going to fix this for me, right? > > > > src/arch/arm/faults.hh > <http://reviews.m5sim.org/r/20/#comment146> > > Why are you specifying the values in this enum? Are they important? > Do they come from some document? A comment might be nice to explain > why. If the values don't matter, then they should probably be removed. > > > > src/arch/arm/insts/macromem.hh > <http://reviews.m5sim.org/r/20/#comment156> > > Fix please > > > > src/arch/arm/insts/macromem.cc > <http://reviews.m5sim.org/r/20/#comment157> > > Fix please > > > > src/arch/arm/insts/mult.hh > <http://reviews.m5sim.org/r/20/#comment158> > > Fix please > > > > src/arch/arm/insts/pred_inst.hh > <http://reviews.m5sim.org/r/20/#comment159> > > Fix please > > > > src/arch/arm/insts/pred_inst.cc > <http://reviews.m5sim.org/r/20/#comment160> > > Fix please > > > > src/arch/arm/insts/static_inst.hh > <http://reviews.m5sim.org/r/20/#comment161> > > Fix please > > > > src/arch/arm/insts/static_inst.cc > <http://reviews.m5sim.org/r/20/#comment162> > > Fix please > > > > src/arch/arm/insts/vfp.cc > <http://reviews.m5sim.org/r/20/#comment163> > > fix please > > > > src/arch/arm/isa.hh > <http://reviews.m5sim.org/r/20/#comment147> > > Another fix here please. > > > > src/arch/arm/isa_traits.hh > <http://reviews.m5sim.org/r/20/#comment148> > > This get resolved? > > > > src/arch/arm/miscregs.hh > <http://reviews.m5sim.org/r/20/#comment149> > > Another fix. > > > > src/arch/arm/miscregs.cc > <http://reviews.m5sim.org/r/20/#comment150> > > How often does this happen? Is there nothing more efficient than this > insane implementation? A table lookup perhaps? > > > > src/arch/arm/predecoder.hh > <http://reviews.m5sim.org/r/20/#comment151> > > Fix please. > > > > src/arch/arm/predecoder.cc > <http://reviews.m5sim.org/r/20/#comment152> > > Fix please > > > > src/arch/arm/process.cc > <http://reviews.m5sim.org/r/20/#comment153> > > Spacing looks messed up at least in reviewboard > > > > src/arch/arm/types.hh > <http://reviews.m5sim.org/r/20/#comment154> > > Fix please > > > > src/arch/arm/utility.hh > <http://reviews.m5sim.org/r/20/#comment155> > > Fix please > > > > src/cpu/simple/base.cc > <http://reviews.m5sim.org/r/20/#comment164> > > This change really require copyright? > > > > src/dev/arm/Versatile.py > <http://reviews.m5sim.org/r/20/#comment165> > > Please remove ## > > > > src/dev/arm/versatile.hh > <http://reviews.m5sim.org/r/20/#comment166> > > Please fix > > > - Nathan > > > On 2010-05-26 20:13:19, Ali Saidi wrote: >> >> ----------------------------------------------------------- >> This is an automatically generated e-mail. To reply, visit: >> http://reviews.m5sim.org/r/20/ >> ----------------------------------------------------------- >> >> (Updated 2010-05-26 20:13:19) >> >> >> Review request for Default. >> >> >> Summary >> ------- >> >> Initial set of patches to improve the M5 support of the ARM ISA. Bundled >> into one large change for review. This change implements the majority of >> thumb, thumb2, and arm instructions and allows the running of all tested >> SPEC2000 benchmarks in atomic mode. >> >> >> Diffs >> ----- >> >> configs/common/cpu2000.py 84bd4089958b >> src/arch/arm/ArmTLB.py 84bd4089958b >> src/arch/arm/SConscript 84bd4089958b >> src/arch/arm/faults.hh 84bd4089958b >> src/arch/arm/faults.cc 84bd4089958b >> src/arch/arm/insts/branch.hh 84bd4089958b >> src/arch/arm/insts/branch.cc 84bd4089958b >> src/arch/arm/insts/macromem.hh 84bd4089958b >> src/arch/arm/insts/macromem.cc PRE-CREATION >> src/arch/arm/insts/mem.hh 84bd4089958b >> src/arch/arm/insts/mem.cc 84bd4089958b >> src/arch/arm/insts/misc.hh PRE-CREATION >> src/arch/arm/insts/misc.cc PRE-CREATION >> src/arch/arm/insts/mult.hh PRE-CREATION >> src/arch/arm/insts/pred_inst.hh 84bd4089958b >> src/arch/arm/insts/pred_inst.cc 84bd4089958b >> src/arch/arm/insts/static_inst.hh 84bd4089958b >> src/arch/arm/insts/static_inst.cc 84bd4089958b >> src/arch/arm/insts/vfp.hh PRE-CREATION >> src/arch/arm/insts/vfp.cc PRE-CREATION >> src/arch/arm/interrupts.hh 84bd4089958b >> src/arch/arm/interrupts.cc 84bd4089958b >> src/arch/arm/intregs.hh 84bd4089958b >> src/arch/arm/isa.hh 84bd4089958b >> src/arch/arm/isa.cc PRE-CREATION >> src/arch/arm/isa/bitfields.isa 84bd4089958b >> src/arch/arm/isa/copyright.txt 84bd4089958b >> src/arch/arm/isa/decoder.isa 84bd4089958b >> src/arch/arm/isa/decoder/arm.isa PRE-CREATION >> src/arch/arm/isa/decoder/decoder.isa PRE-CREATION >> src/arch/arm/isa/decoder/thumb.isa PRE-CREATION >> src/arch/arm/isa/formats/basic.isa 84bd4089958b >> src/arch/arm/isa/formats/branch.isa 84bd4089958b >> src/arch/arm/isa/formats/breakpoint.isa PRE-CREATION >> src/arch/arm/isa/formats/data.isa PRE-CREATION >> src/arch/arm/isa/formats/formats.isa 84bd4089958b >> src/arch/arm/isa/formats/fp.isa 84bd4089958b >> src/arch/arm/isa/formats/macromem.isa 84bd4089958b >> src/arch/arm/isa/formats/mem.isa 84bd4089958b >> src/arch/arm/isa/formats/misc.isa PRE-CREATION >> src/arch/arm/isa/formats/mult.isa PRE-CREATION >> src/arch/arm/isa/formats/pred.isa 84bd4089958b >> src/arch/arm/isa/formats/uncond.isa PRE-CREATION >> src/arch/arm/isa/formats/unimp.isa 84bd4089958b >> src/arch/arm/isa/formats/unknown.isa 84bd4089958b >> src/arch/arm/isa/formats/util.isa 84bd4089958b >> src/arch/arm/isa/includes.isa 84bd4089958b >> src/arch/arm/isa/insts/basic.isa PRE-CREATION >> src/arch/arm/isa/insts/branch.isa PRE-CREATION >> src/arch/arm/isa/insts/data.isa PRE-CREATION >> src/arch/arm/isa/insts/div.isa PRE-CREATION >> src/arch/arm/isa/insts/fp.isa PRE-CREATION >> src/arch/arm/isa/insts/insts.isa PRE-CREATION >> src/arch/arm/isa/insts/ldr.isa PRE-CREATION >> src/arch/arm/isa/insts/macromem.isa PRE-CREATION >> src/arch/arm/isa/insts/mem.isa PRE-CREATION >> src/arch/arm/isa/insts/misc.isa PRE-CREATION >> src/arch/arm/isa/insts/mult.isa PRE-CREATION >> src/arch/arm/isa/insts/str.isa PRE-CREATION >> src/arch/arm/isa/insts/swap.isa PRE-CREATION >> src/arch/arm/isa/main.isa 84bd4089958b >> src/arch/arm/isa/operands.isa 84bd4089958b >> src/arch/arm/isa/templates/basic.isa PRE-CREATION >> src/arch/arm/isa/templates/branch.isa PRE-CREATION >> src/arch/arm/isa/templates/macromem.isa PRE-CREATION >> src/arch/arm/isa/templates/mem.isa PRE-CREATION >> src/arch/arm/isa/templates/misc.isa PRE-CREATION >> src/arch/arm/isa/templates/mult.isa PRE-CREATION >> src/arch/arm/isa/templates/pred.isa PRE-CREATION >> src/arch/arm/isa/templates/templates.isa PRE-CREATION >> src/arch/arm/isa/templates/vfp.isa PRE-CREATION >> src/arch/arm/isa_traits.hh 84bd4089958b >> src/arch/arm/linux/linux.hh 84bd4089958b >> src/arch/arm/linux/linux.cc 84bd4089958b >> src/arch/arm/linux/process.hh 84bd4089958b >> src/arch/arm/linux/process.cc 84bd4089958b >> src/arch/arm/miscregs.hh 84bd4089958b >> src/arch/arm/miscregs.cc PRE-CREATION >> src/arch/arm/nativetrace.cc 84bd4089958b >> src/arch/arm/pagetable.hh 84bd4089958b >> src/arch/arm/pagetable.cc 84bd4089958b >> src/arch/arm/predecoder.hh 84bd4089958b >> src/arch/arm/predecoder.cc PRE-CREATION >> src/arch/arm/process.hh 84bd4089958b >> src/arch/arm/process.cc 84bd4089958b >> src/arch/arm/registers.hh 84bd4089958b >> src/arch/arm/table_walker.hh PRE-CREATION >> src/arch/arm/table_walker.cc PRE-CREATION >> src/arch/arm/tlb.hh 84bd4089958b >> src/arch/arm/tlb.cc 84bd4089958b >> src/arch/arm/types.hh 84bd4089958b >> src/arch/arm/utility.hh 84bd4089958b >> src/arch/arm/utility.cc 84bd4089958b >> src/arch/isa_parser.py 84bd4089958b >> src/base/loader/elf_object.cc 84bd4089958b >> src/base/loader/object_file.hh 84bd4089958b >> src/cpu/BaseCPU.py 84bd4089958b >> src/cpu/exetrace.cc 84bd4089958b >> src/cpu/simple/base.cc 84bd4089958b >> src/cpu/simple_thread.hh 84bd4089958b >> src/dev/arm/SConscript 84bd4089958b >> src/dev/arm/Versatile.py 84bd4089958b >> src/dev/arm/versatile.hh 84bd4089958b >> src/dev/arm/versatile.cc 84bd4089958b >> src/dev/copy_engine.cc 84bd4089958b >> src/dev/io_device.hh 84bd4089958b >> src/dev/io_device.cc 84bd4089958b >> src/sim/process.cc 84bd4089958b >> tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini >> 84bd4089958b >> tests/quick/00.hello/ref/arm/linux/simple-atomic/simerr 84bd4089958b >> tests/quick/00.hello/ref/arm/linux/simple-atomic/simout 84bd4089958b >> tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt >> 84bd4089958b >> util/statetrace/arch/tracechild_arm.hh 84bd4089958b >> util/statetrace/arch/tracechild_arm.cc 84bd4089958b >> util/statetrace/statetrace.cc 84bd4089958b >> >> Diff: http://reviews.m5sim.org/r/20/diff >> >> >> Testing >> ------- >> >> >> Thanks, >> >> Ali >> >> > > _______________________________________________ > m5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/m5-dev _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
