Is it possible that the speculatively fetched instructions can cause programming assertions to fail? Until a branch is resolved, whatever (even non-instructions) in the predicted path could be fetched and decoded. Can't assertions on instruction sanity fail for those?
I am trying to make O3 CPU model for ARM working. In many cases the first instruction is a branch followed by a interrupt vector table. I was wondering if such cases exist for other CPU models and if it is, handled how. Thanks, Min
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