changeset 6b72468fbad3 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=6b72468fbad3
description:
cache: fix longstanding prefetcher bug
Thanks to Joe Gross for pointing this out (again?).
Apologies to anyone who pointed it out earlier and
we didn't listen.
diffstat:
src/mem/cache/cache_impl.hh | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diffs (12 lines):
diff -r 91994f36de7f -r 6b72468fbad3 src/mem/cache/cache_impl.hh
--- a/src/mem/cache/cache_impl.hh Wed Jun 23 00:53:17 2010 +0100
+++ b/src/mem/cache/cache_impl.hh Tue Jun 22 21:29:43 2010 -0700
@@ -1308,7 +1308,7 @@
// fall through... no pending requests. Try a prefetch.
assert(!miss_mshr && !write_mshr);
- if (!mshrQueue.isFull()) {
+ if (prefetcher && !mshrQueue.isFull()) {
// If we have a miss queue slot, we can try a prefetch
PacketPtr pkt = prefetcher->getPacket();
if (pkt) {
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev
