changeset e3311623d9f0 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=e3311623d9f0
description:
inorder: stall signal handling
remove stall only when necessary
add debugging printfs
diffstat:
src/cpu/inorder/pipeline_stage.cc | 22 +++++++++++++++++++---
1 files changed, 19 insertions(+), 3 deletions(-)
diffs (44 lines):
diff -r 88cc2dc9472c -r e3311623d9f0 src/cpu/inorder/pipeline_stage.cc
--- a/src/cpu/inorder/pipeline_stage.cc Wed Jun 23 18:14:59 2010 -0400
+++ b/src/cpu/inorder/pipeline_stage.cc Wed Jun 23 18:15:23 2010 -0400
@@ -233,8 +233,21 @@
void
PipelineStage::removeStalls(ThreadID tid)
{
- for (int stNum = 0; stNum < NumStages; stNum++) {
- stalls[tid].stage[stNum] = false;
+ for (int st_num = 0; st_num < NumStages; st_num++) {
+ if (stalls[tid].stage[st_num] == true) {
+ DPRINTF(InOrderStage, "Removing stall from stage %i.\n", st_num);
+ stalls[tid].stage[st_num] = false;
+ }
+
+ if (toPrevStages->stageBlock[st_num][tid] == true) {
+ DPRINTF(InOrderStage, "Removing pending block from stage %i.\n",
st_num);
+ toPrevStages->stageBlock[st_num][tid] = false;
+ }
+
+ if (fromNextStages->stageBlock[st_num][tid] == true) {
+ DPRINTF(InOrderStage, "Removing pending block from stage %i.\n",
st_num);
+ fromNextStages->stageBlock[st_num][tid] = false;
+ }
}
stalls[tid].resources.clear();
}
@@ -626,12 +639,15 @@
// Check for Stage Blocking Signal
if (fromNextStages->stageBlock[stage_idx][tid]) {
+ DPRINTF(InOrderStage, "[tid:%i] Stall from stage %i set.\n", tid,
+ stage_idx);
stalls[tid].stage[stage_idx] = true;
}
// Check for Stage Unblocking Signal
if (fromNextStages->stageUnblock[stage_idx][tid]) {
- //assert(fromNextStages->stageBlock[stage_idx][tid]);
+ DPRINTF(InOrderStage, "[tid:%i] Stall from stage %i unset.\n", tid,
+ stage_idx);
stalls[tid].stage[stage_idx] = false;
}
}
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