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Review request for Default. Summary ------- Sim: When one CPU is taking over from another, the new CPU's memory is only connected up if it's not connected to something already. However, when sharing caches between several CPUs and repeatedly switching between them, the CPU thinks it is connected up when it actually isn't. To rectify this, provide a new parameter to the takeOverFrom function that forces memory to be connected up. Diffs ----- src/cpu/base.hh 249f174e6f37 src/cpu/base.cc 249f174e6f37 src/cpu/checker/cpu.hh 249f174e6f37 src/cpu/checker/cpu_impl.hh 249f174e6f37 src/cpu/o3/cpu.hh 249f174e6f37 src/cpu/o3/cpu.cc 249f174e6f37 src/cpu/simple/atomic.hh 249f174e6f37 src/cpu/simple/atomic.cc 249f174e6f37 src/cpu/simple/timing.hh 249f174e6f37 src/cpu/simple/timing.cc 249f174e6f37 src/python/m5/SimObject.py 249f174e6f37 src/python/m5/simulate.py 249f174e6f37 src/python/swig/sim_object.i 249f174e6f37 src/sim/sim_object.hh 249f174e6f37 src/sim/sim_object.cc 249f174e6f37 Diff: http://reviews.m5sim.org/r/49/diff Testing ------- Thanks, Timothy _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
