changeset be7c22eb8c20 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=be7c22eb8c20
description:
ARM: Make an SRS instruction with a bad mode cause an undefined
instruction fault.
diffstat:
src/arch/arm/isa/formats/mem.isa | 2 ++
src/arch/arm/isa/formats/uncond.isa | 2 ++
2 files changed, 4 insertions(+), 0 deletions(-)
diffs (24 lines):
diff -r fbc62b421fa0 -r be7c22eb8c20 src/arch/arm/isa/formats/mem.isa
--- a/src/arch/arm/isa/formats/mem.isa Tue Jul 13 22:41:47 2010 -0700
+++ b/src/arch/arm/isa/formats/mem.isa Thu Jul 15 02:11:56 2010 -0700
@@ -282,6 +282,8 @@
}
} else {
const uint32_t mode = bits(machInst, 4, 0);
+ if (badMode((OperatingMode)mode))
+ return new Unknown(machInst);
if (!add && !wb) {
return new %(srs)s(machInst, mode,
SrsOp::DecrementBefore, wb);
diff -r fbc62b421fa0 -r be7c22eb8c20 src/arch/arm/isa/formats/uncond.isa
--- a/src/arch/arm/isa/formats/uncond.isa Tue Jul 13 22:41:47 2010 -0700
+++ b/src/arch/arm/isa/formats/uncond.isa Thu Jul 15 02:11:56 2010 -0700
@@ -166,6 +166,8 @@
const uint32_t val = ((machInst >> 20) & 0x5);
if (val == 0x4) {
const uint32_t mode = bits(machInst, 4, 0);
+ if (badMode((OperatingMode)mode))
+ return new Unknown(machInst);
switch (bits(machInst, 24, 21)) {
case 0x2:
return new %(srs)s(machInst, mode,
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