ARM has an instruction that clears the lock flag (CLREX). To implement that in physical memory, it's easy enough, on the other hand with the cache it requires calling clearLoadLocks() on every block in the cache.
Ali On Thu, 15 Jul 2010 16:01:09 -0700, nathan binkert <[email protected]> wrote: >> You're right that it could be done either way. I think the rationale >> is that this way you don't need to search a list to see if your >> address is on it. If the common case is that there are no locked >> blocks in the entire cache though then that's not a big deal since the >> list will be empty anyway. I can't think of any other reason. > > Why do you need a list of lock addresses? The only reason I can think > of is because of multiple threads. Is that what you're referring to? > I guess the other issue is that the lock address would have to be > checked on all stores in the system which could be a pain. Another > reason is that you're already accessing the tag for coherence > operations, so you might as well put the lock info there. You could > for example update MESI to have a "locked exclusive" or "locked > modified" state. > > > Nate > _______________________________________________ > m5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/m5-dev _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
