changeset 3bd51d6ac9ef in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=3bd51d6ac9ef
description:
O3CPU: Fix a bug where stores in the cpu where never marked as split.
diffstat:
src/cpu/o3/lsq_unit.hh | 6 ++++++
1 files changed, 6 insertions(+), 0 deletions(-)
diffs (16 lines):
diff -r 02b471d9d400 -r 3bd51d6ac9ef src/cpu/o3/lsq_unit.hh
--- a/src/cpu/o3/lsq_unit.hh Thu Jul 22 18:47:52 2010 +0100
+++ b/src/cpu/o3/lsq_unit.hh Thu Jul 22 18:52:02 2010 +0100
@@ -822,6 +822,12 @@
storeQueue[store_idx].sreqLow = sreqLow;
storeQueue[store_idx].sreqHigh = sreqHigh;
storeQueue[store_idx].size = sizeof(T);
+
+ // Split stores can only occur in ISAs with unaligned memory accesses. If
+ // a store request has been split, sreqLow and sreqHigh will be non-null.
+ if (TheISA::HasUnalignedMemAcc && sreqLow) {
+ storeQueue[store_idx].isSplit = true;
+ }
assert(sizeof(T) <= sizeof(storeQueue[store_idx].data));
T gData = htog(data);
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev
