changeset ffac9df60637 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=ffac9df60637
description:
Power: The condition register should be set or cleared upon a system
call
return to indicate success or failure.
diffstat:
src/arch/power/miscregs.hh | 7 ++++++-
src/arch/power/process.cc | 7 +++++++
2 files changed, 13 insertions(+), 1 deletions(-)
diffs (33 lines):
diff -r bd104adbf04d -r ffac9df60637 src/arch/power/miscregs.hh
--- a/src/arch/power/miscregs.hh Thu Jul 22 18:54:37 2010 +0100
+++ b/src/arch/power/miscregs.hh Thu Jul 22 18:54:37 2010 +0100
@@ -44,7 +44,12 @@
};
BitUnion32(Cr)
- Bitfield<31,28> cr0;
+ SubBitUnion(cr0, 31, 28)
+ Bitfield<31> lt;
+ Bitfield<30> gt;
+ Bitfield<29> eq;
+ Bitfield<28> so;
+ EndSubBitUnion(cr0)
Bitfield<27,24> cr1;
EndBitUnion(Cr)
diff -r bd104adbf04d -r ffac9df60637 src/arch/power/process.cc
--- a/src/arch/power/process.cc Thu Jul 22 18:54:37 2010 +0100
+++ b/src/arch/power/process.cc Thu Jul 22 18:54:37 2010 +0100
@@ -284,5 +284,12 @@
PowerLiveProcess::setSyscallReturn(ThreadContext *tc,
SyscallReturn return_value)
{
+ Cr cr = tc->readIntReg(INTREG_CR);
+ if (return_value.successful()) {
+ cr.cr0.so = 0;
+ } else {
+ cr.cr0.so = 1;
+ }
+ tc->setIntReg(INTREG_CR, cr);
tc->setIntReg(ReturnValueReg, return_value.value());
}
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