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Review request for Default. Summary ------- TimingCPU: REPOST: Request::NO_ACCESS bypass in completeDataAccess ./cpu/simple/timing.cc: fix for x86 CDA microop - since CDA doesn't read or update memory, completeDataAccess needs to handle the case where the current status of the CPU is _status = Running caused by a request NO_ACCESS Discarded previous review request (SIMPLE TIMING: when a request is NO_ACCESS (x86 CDA microinstruction), TimingSimpleCPU::completeDataAccess must still complete) Diffs ----- src/cpu/simple/timing.cc a75564db03c3 Diff: http://reviews.m5sim.org/r/66/diff Testing ------- Thanks, Joel _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
