> On 2010-07-29 08:32:04, Steve Reinhardt wrote: > > Hi Tim, > > > > Sorry for the long delay on this... this looks great to me, with one minor > > issue: I see you changed the lookup/update method names to > > BPLookup/BPUpdate etc. The lower-case names are the ones we want to keep > > though, since they follow the M5 style > > (http://m5sim.org/wiki/index.php/Coding_Style#Naming); the BPFoo names were > > violating the style to begin with. > > > > I think there were two different interfaces, an external one to the CPU and > > a more internal one, with different names, and since you are getting rid of > > that layer of indirection you had to pick one, and you just happened to > > pick the worse one instead of the better one :-). > > > > Steve
Ah, typical! I'll fix this when I've integrated the in-order changes too. - Timothy ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/47/#review113 ----------------------------------------------------------- On 2010-07-16 13:17:58, Timothy Jones wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/47/ > ----------------------------------------------------------- > > (Updated 2010-07-16 13:17:58) > > > Review request for Default. > > > Summary > ------- > > BranchPred: Take the branch predictor out of O3CPU and make it a stand-alone > SimObject. This then allows the same branch predictor to be shared amongst > several CPUs. > > This patch is unfinished. I would like to take the branch predictor out of > the inorder CPU as well, but want comments on whether this is the best > approach to take first. > > > Diffs > ----- > > src/cpu/o3/O3CPU.py 249f174e6f37 > src/cpu/o3/SConscript 249f174e6f37 > src/cpu/o3/bpred_unit.hh 249f174e6f37 > src/cpu/o3/bpred_unit.cc 249f174e6f37 > src/cpu/o3/bpred_unit_impl.hh 249f174e6f37 > src/cpu/o3/cpu_builder.cc 249f174e6f37 > src/cpu/o3/cpu_policy.hh 249f174e6f37 > src/cpu/o3/fetch.hh 249f174e6f37 > src/cpu/o3/fetch_impl.hh 249f174e6f37 > src/cpu/o3/sat_counter.hh 249f174e6f37 > src/cpu/o3/sat_counter.cc 249f174e6f37 > src/cpu/pred/2bit_local.hh 249f174e6f37 > src/cpu/pred/2bit_local.cc 249f174e6f37 > src/cpu/pred/SConscript 249f174e6f37 > src/cpu/pred/bpred_unit.hh PRE-CREATION > src/cpu/pred/bpred_unit.cc PRE-CREATION > src/cpu/pred/bpred_unit_impl.hh PRE-CREATION > src/cpu/pred/ras.hh 249f174e6f37 > src/cpu/pred/tournament.hh 249f174e6f37 > src/cpu/pred/tournament.cc 249f174e6f37 > > Diff: http://reviews.m5sim.org/r/47/diff > > > Testing > ------- > > > Thanks, > > Timothy > > _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
