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Review request for Default. Summary ------- ruby: Reduced ruby latencies The previous slower ruby latencies created a mismatch between the faster M5 cpu models and the much slower ruby memory system. Specifically smp interrupts were much slower and infrequent, as well as cpus moving in and out of spin locks. The result was many cpus were idle for large periods of time. These changes fix the latency mismatch. Diffs ----- configs/common/Options.py a75564db03c3 configs/example/ruby_se.py a75564db03c3 configs/ruby/MOESI_CMP_token.py PRE-CREATION configs/ruby/MOESI_hammer.py PRE-CREATION src/mem/protocol/MOESI_CMP_token-L1cache.sm a75564db03c3 src/mem/protocol/MOESI_CMP_token-L2cache.sm a75564db03c3 src/mem/protocol/MOESI_CMP_token-dir.sm a75564db03c3 src/mem/protocol/MOESI_hammer-cache.sm a75564db03c3 src/mem/protocol/MOESI_hammer-dir.sm a75564db03c3 Diff: http://reviews.m5sim.org/r/99/diff Testing ------- Thanks, Brad _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
