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http://reviews.m5sim.org/r/116/#review143
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src/mem/slicc/ast/StallAndWaitStatementAST.py
<http://reviews.m5sim.org/r/116/#comment283>

    Shouldn't the copyright only be AMD?



src/mem/slicc/ast/WakeUpDependentsStatementAST.py
<http://reviews.m5sim.org/r/116/#comment284>

    Shouldn't the copyright only be AMD?


- Nathan


On 2010-08-05 21:49:59, Brad Beckmann wrote:
> 
> -----------------------------------------------------------
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/116/
> -----------------------------------------------------------
> 
> (Updated 2010-08-05 21:49:59)
> 
> 
> Review request for Default.
> 
> 
> Summary
> -------
> 
> ruby: Stall and wait input messages instead of recycling
> 
> This patch allows messages to be stalled in their input buffers and wait
> until a corresponding address changes state.  In order to make this work,
> all in_ports must be ranked in order of dependence and those in_ports that
> may unblock an address, must wake up the stalled messages.  Alot of this
> complexity is handled in slicc and the specification files simply
> annotate the in_ports.
> 
> 
> Diffs
> -----
> 
>   src/mem/protocol/MOESI_hammer-dir.sm a75564db03c3 
>   src/mem/ruby/buffers/MessageBuffer.hh a75564db03c3 
>   src/mem/ruby/buffers/MessageBuffer.cc a75564db03c3 
>   src/mem/slicc/ast/InPortDeclAST.py a75564db03c3 
>   src/mem/slicc/ast/PeekStatementAST.py a75564db03c3 
>   src/mem/slicc/ast/StallAndWaitStatementAST.py PRE-CREATION 
>   src/mem/slicc/ast/WakeUpDependentsStatementAST.py PRE-CREATION 
>   src/mem/slicc/ast/__init__.py a75564db03c3 
>   src/mem/slicc/parser.py a75564db03c3 
>   src/mem/slicc/symbols/StateMachine.py a75564db03c3 
> 
> Diff: http://reviews.m5sim.org/r/116/diff
> 
> 
> Testing
> -------
> 
> 
> Thanks,
> 
> Brad
> 
>

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