----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/192/#review197 -----------------------------------------------------------
Is this really desired behavior? Aren't there cases when having a software prefetch prefetching results into the TLB is a good idea? To be honest I don't know what our processors do; I'll try and find out. - Steve On 2010-08-13 10:16:34, Ali Saidi wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/192/ > ----------------------------------------------------------- > > (Updated 2010-08-13 10:16:34) > > > Review request for Default. > > > Summary > ------- > > ARM: Make sure that software prefetch instructions can't change the state of > the TLB > > > Diffs > ----- > > src/arch/arm/faults.hh 3c48b2b3cb83 > src/arch/arm/table_walker.cc 3c48b2b3cb83 > src/arch/arm/tlb.cc 3c48b2b3cb83 > src/mem/cache/cache_impl.hh 3c48b2b3cb83 > > Diff: http://reviews.m5sim.org/r/192/diff > > > Testing > ------- > > > Thanks, > > Ali > > _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
