changeset fe90827a663f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=fe90827a663f
description:
sim: move iterating over SimObjects into Python.
diffstat:
src/python/m5/SimObject.py | 46 +++++------------------
src/python/m5/core.py | 8 ----
src/python/m5/simulate.py | 33 ++++++++++------
src/python/m5/stats.py | 5 ++
src/python/swig/core.i | 4 --
src/python/swig/pyobject.hh | 17 ---------
src/python/swig/sim_object.i | 6 +++
src/sim/sim_object.cc | 82 --------------------------------------------
src/sim/sim_object.hh | 8 ----
9 files changed, 42 insertions(+), 167 deletions(-)
diffs (truncated from 417 to 300 lines):
diff -r 4bb5f5207617 -r fe90827a663f src/python/m5/SimObject.py
--- a/src/python/m5/SimObject.py Tue Aug 17 05:06:22 2010 -0700
+++ b/src/python/m5/SimObject.py Tue Aug 17 05:08:50 2010 -0700
@@ -530,7 +530,8 @@
# If the attribute exists on the C++ object, transparently
# forward the reference there. This is typically used for
# SWIG-wrapped methods such as init(), regStats(),
- # regFormulas(), resetStats(), and startup().
+ # regFormulas(), resetStats(), startup(), drain(), and
+ # resume().
if self._ccObject and hasattr(self._ccObject, attr):
return getattr(self._ccObject, attr)
@@ -660,7 +661,7 @@
def unproxy(self, base):
return self
- def unproxy_all(self):
+ def unproxyParams(self):
for param in self._params.iterkeys():
value = self._values.get(param)
if value != None and isproxy(value):
@@ -681,12 +682,6 @@
if port != None:
port.unproxy(self)
- # Unproxy children in sorted order for determinism also.
- child_names = self._children.keys()
- child_names.sort()
- for child in child_names:
- self._children[child].unproxy_all()
-
def print_ini(self, ini_file):
print >>ini_file, '[' + self.path() + ']' # .ini section header
@@ -717,9 +712,6 @@
print >>ini_file # blank line between objects
- for child in child_names:
- self._children[child].print_ini(ini_file)
-
def getCCParams(self):
if self._ccParams:
return self._ccParams
@@ -774,39 +766,25 @@
% self.path()
return self._ccObject
- # Call C++ to create C++ object corresponding to this object and
- # (recursively) all its children
+ def descendants(self):
+ yield self
+ for child in self._children.itervalues():
+ for obj in child.descendants():
+ yield obj
+
+ # Call C++ to create C++ object corresponding to this object
def createCCObject(self):
self.getCCParams()
self.getCCObject() # force creation
- for child in self._children.itervalues():
- child.createCCObject()
def getValue(self):
return self.getCCObject()
# Create C++ port connections corresponding to the connections in
- # _port_refs (& recursively for all children)
+ # _port_refs
def connectPorts(self):
for portRef in self._port_refs.itervalues():
portRef.ccConnect()
- for child in self._children.itervalues():
- child.connectPorts()
-
- def startDrain(self, drain_event, recursive):
- count = 0
- if isinstance(self, SimObject):
- count += self._ccObject.drain(drain_event)
- if recursive:
- for child in self._children.itervalues():
- count += child.startDrain(drain_event, True)
- return count
-
- def resume(self):
- if isinstance(self, SimObject):
- self._ccObject.resume()
- for child in self._children.itervalues():
- child.resume()
def getMemoryMode(self):
if not isinstance(self, m5.objects.System):
@@ -820,8 +798,6 @@
# setMemoryMode directly from self._ccObject results in calling
# SimObject::setMemoryMode, not the System::setMemoryMode
self._ccObject.setMemoryMode(mode)
- for child in self._children.itervalues():
- child.changeTiming(mode)
def takeOverFrom(self, old_cpu):
self._ccObject.takeOverFrom(old_cpu._ccObject)
diff -r 4bb5f5207617 -r fe90827a663f src/python/m5/core.py
--- a/src/python/m5/core.py Tue Aug 17 05:06:22 2010 -0700
+++ b/src/python/m5/core.py Tue Aug 17 05:08:50 2010 -0700
@@ -27,14 +27,6 @@
# Authors: Nathan Binkert
import internal
-from internal.core import initAll, regAllStats
def setOutputDir(dir):
internal.core.setOutputDir(dir)
-
-def initAll():
- internal.core.initAll()
-
-def regAllStats():
- internal.core.regAllStats()
-
diff -r 4bb5f5207617 -r fe90827a663f src/python/m5/simulate.py
--- a/src/python/m5/simulate.py Tue Aug 17 05:06:22 2010 -0700
+++ b/src/python/m5/simulate.py Tue Aug 17 05:08:50 2010 -0700
@@ -55,25 +55,29 @@
# we need to fix the global frequency
ticks.fixGlobalFrequency()
- root.unproxy_all()
+ # Unproxy in sorted order for determinism
+ for obj in root.descendants(): obj.unproxyParams()
if options.dump_config:
ini_file = file(os.path.join(options.outdir, options.dump_config), 'w')
- root.print_ini(ini_file)
+ # Print ini sections in sorted order for easier diffing
+ for obj in sorted(root.descendants(), key=lambda o: o.path()):
+ obj.print_ini(ini_file)
ini_file.close()
# Initialize the global statistics
stats.initSimStats()
# Create the C++ sim objects and connect ports
- root.createCCObject()
- root.connectPorts()
+ for obj in root.descendants(): obj.createCCObject()
+ for obj in root.descendants(): obj.connectPorts()
# Do a second pass to finish initializing the sim objects
- core.initAll()
+ for obj in root.descendants(): obj.init()
# Do a third pass to initialize statistics
- core.regAllStats()
+ for obj in root.descendants(): obj.regStats()
+ for obj in root.descendants(): obj.regFormulas()
# We're done registering statistics. Enable the stats package now.
stats.enable()
@@ -97,7 +101,8 @@
global need_resume, need_startup
if need_startup:
- internal.core.startupAll()
+ root = objects.Root.getInstance()
+ for obj in root.descendants(): obj.startup()
need_startup = False
for root in need_resume:
@@ -129,10 +134,10 @@
def drain(root):
all_drained = False
drain_event = internal.event.createCountedDrain()
- unready_objects = root.startDrain(drain_event, True)
+ unready_objs = sum(obj.drain(drain_event) for obj in root.descendants())
# If we've got some objects that can't drain immediately, then simulate
- if unready_objects > 0:
- drain_event.setCount(unready_objects)
+ if unready_objs > 0:
+ drain_event.setCount(unready_objs)
simulate()
else:
all_drained = True
@@ -140,7 +145,7 @@
return all_drained
def resume(root):
- root.resume()
+ for obj in root.descendants(): obj.resume()
def checkpoint(dir):
root = objects.Root.getInstance()
@@ -165,7 +170,8 @@
if system.getMemoryMode() != objects.params.atomic:
doDrain(system)
print "Changing memory mode to atomic"
- system.changeTiming(objects.params.atomic)
+ for obj in system.descendants():
+ obj.changeTiming(objects.params.atomic)
def changeToTiming(system):
if not isinstance(system, (objects.Root, objects.System)):
@@ -175,7 +181,8 @@
if system.getMemoryMode() != objects.params.timing:
doDrain(system)
print "Changing memory mode to timing"
- system.changeTiming(objects.params.timing)
+ for obj in system.descendants():
+ obj.changeTiming(objects.params.timing)
def switchCpus(cpuList):
print "switching cpus"
diff -r 4bb5f5207617 -r fe90827a663f src/python/m5/stats.py
--- a/src/python/m5/stats.py Tue Aug 17 05:06:22 2010 -0700
+++ b/src/python/m5/stats.py Tue Aug 17 05:08:50 2010 -0700
@@ -29,6 +29,7 @@
import internal
from internal.stats import StatEvent as event
+from objects import Root
def initText(filename, desc=True):
internal.stats.initText(filename, desc)
@@ -56,4 +57,8 @@
internal.stats.dump()
def reset():
+ # call reset stats on all SimObjects
+ root = Root.getInstance()
+ for obj in root.descendants(): obj.resetStats()
+ # call any other registered stats reset callbacks
internal.stats.reset()
diff -r 4bb5f5207617 -r fe90827a663f src/python/swig/core.i
--- a/src/python/swig/core.i Tue Aug 17 05:06:22 2010 -0700
+++ b/src/python/swig/core.i Tue Aug 17 05:08:50 2010 -0700
@@ -78,10 +78,6 @@
void serializeAll(const std::string &cpt_dir);
void unserializeAll(const std::string &cpt_dir);
-void initAll();
-void regAllStats();
-void startupAll();
-
bool want_warn, warn_verbose;
bool want_info, info_verbose;
bool want_hack, hack_verbose;
diff -r 4bb5f5207617 -r fe90827a663f src/python/swig/pyobject.hh
--- a/src/python/swig/pyobject.hh Tue Aug 17 05:06:22 2010 -0700
+++ b/src/python/swig/pyobject.hh Tue Aug 17 05:08:50 2010 -0700
@@ -45,17 +45,6 @@
int connectPorts(SimObject *o1, const std::string &name1, int i1,
SimObject *o2, const std::string &name2, int i2);
-inline void
-initAll()
-{
- SimObject::initAll();
-}
-
-inline void
-regAllStats()
-{
- SimObject::regAllStats();
-}
inline void
serializeAll(const std::string &cpt_dir)
@@ -68,9 +57,3 @@
{
Serializable::unserializeAll(cpt_dir);
}
-
-inline void
-startupAll()
-{
- SimObject::startupAll();
-}
diff -r 4bb5f5207617 -r fe90827a663f src/python/swig/sim_object.i
--- a/src/python/swig/sim_object.i Tue Aug 17 05:06:22 2010 -0700
+++ b/src/python/swig/sim_object.i Tue Aug 17 05:08:50 2010 -0700
@@ -50,6 +50,12 @@
Drained
};
+ void init();
+ void regStats();
+ void regFormulas();
+ void resetStats();
+ void startup();
+
unsigned int drain(Event *drain_event);
void resume();
void switchOut();
diff -r 4bb5f5207617 -r fe90827a663f src/sim/sim_object.cc
--- a/src/sim/sim_object.cc Tue Aug 17 05:06:22 2010 -0700
+++ b/src/sim/sim_object.cc Tue Aug 17 05:08:50 2010 -0700
@@ -97,76 +97,6 @@
}
//
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