changeset 1e1f63dfd130 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=1e1f63dfd130
description:
        config: Improve ruby simobject names

        This patch attaches ruby objects to the system before the topology is
        created so that their simobject names read their meaningful variable
        names instead of their topology name.

diffstat:

 configs/example/memtest-ruby.py     |   2 +-
 configs/example/ruby_fs.py          |   2 +-
 configs/example/ruby_se.py          |   2 +-
 configs/example/rubytest.py         |   2 +-
 configs/ruby/MESI_CMP_directory.py  |  25 +++++++++++++++++--------
 configs/ruby/MI_example.py          |  27 +++++++++++++++++----------
 configs/ruby/MOESI_CMP_directory.py |  24 ++++++++++++++++--------
 configs/ruby/MOESI_CMP_token.py     |  29 +++++++++++++++++++----------
 configs/ruby/MOESI_hammer.py        |  27 +++++++++++++++++----------
 configs/ruby/Ruby.py                |   7 ++++---
 10 files changed, 94 insertions(+), 53 deletions(-)

diffs (truncated from 476 to 300 lines):

diff -r 86c3bf056a0d -r 1e1f63dfd130 configs/example/memtest-ruby.py
--- a/configs/example/memtest-ruby.py   Fri Aug 20 11:46:11 2010 -0700
+++ b/configs/example/memtest-ruby.py   Fri Aug 20 11:46:11 2010 -0700
@@ -111,7 +111,7 @@
                 funcmem = PhysicalMemory(),
                 physmem = PhysicalMemory())
 
-system.ruby = Ruby.create_system(options, system.physmem)
+system.ruby = Ruby.create_system(options, system)
 
 assert(len(cpus) == len(system.ruby.cpu_ruby_ports))
 
diff -r 86c3bf056a0d -r 1e1f63dfd130 configs/example/ruby_fs.py
--- a/configs/example/ruby_fs.py        Fri Aug 20 11:46:11 2010 -0700
+++ b/configs/example/ruby_fs.py        Fri Aug 20 11:46:11 2010 -0700
@@ -113,7 +113,7 @@
 system = makeLinuxAlphaRubySystem(test_mem_mode, bm[0])
 
 system.ruby = Ruby.create_system(options,
-                                 system.physmem,
+                                 system,
                                  system.piobus,
                                  system.dma_devices)
 
diff -r 86c3bf056a0d -r 1e1f63dfd130 configs/example/ruby_se.py
--- a/configs/example/ruby_se.py        Fri Aug 20 11:46:11 2010 -0700
+++ b/configs/example/ruby_se.py        Fri Aug 20 11:46:11 2010 -0700
@@ -150,7 +150,7 @@
 system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
                 physmem = PhysicalMemory())
 
-system.ruby = Ruby.create_system(options, system.physmem)
+system.ruby = Ruby.create_system(options, system)
 
 assert(options.num_cpus == len(system.ruby.cpu_ruby_ports))
 
diff -r 86c3bf056a0d -r 1e1f63dfd130 configs/example/rubytest.py
--- a/configs/example/rubytest.py       Fri Aug 20 11:46:11 2010 -0700
+++ b/configs/example/rubytest.py       Fri Aug 20 11:46:11 2010 -0700
@@ -92,7 +92,7 @@
 #
 system = System(physmem = PhysicalMemory())
 
-system.ruby = Ruby.create_system(options, system.physmem)
+system.ruby = Ruby.create_system(options, system)
 
 assert(options.num_cpus == len(system.ruby.cpu_ruby_ports))
 
diff -r 86c3bf056a0d -r 1e1f63dfd130 configs/ruby/MESI_CMP_directory.py
--- a/configs/ruby/MESI_CMP_directory.py        Fri Aug 20 11:46:11 2010 -0700
+++ b/configs/ruby/MESI_CMP_directory.py        Fri Aug 20 11:46:11 2010 -0700
@@ -47,7 +47,7 @@
 def define_options(parser):
     return
 
-def create_system(options, phys_mem, piobus, dma_devices):
+def create_system(options, system, piobus, dma_devices):
     
     if buildEnv['PROTOCOL'] != 'MESI_CMP_directory':
         panic("This script requires the MESI_CMP_directory protocol to be 
built.")
@@ -81,8 +81,8 @@
         cpu_seq = RubySequencer(version = i,
                                 icache = l1i_cache,
                                 dcache = l1d_cache,
-                                physMemPort = phys_mem.port,
-                                physmem = phys_mem)
+                                physMemPort = system.physmem.port,
+                                physmem = system.physmem)
 
         if piobus != None:
             cpu_seq.pio_port = piobus.port
@@ -92,7 +92,11 @@
                                       L1IcacheMemory = l1i_cache,
                                       L1DcacheMemory = l1d_cache,
                                       l2_select_num_bits = \
-                                        math.log(options.num_l2caches, 2))
+                                        math.log(options.num_l2caches,
+                                                 2))
+
+        exec("system.l1_cntrl%d = l1_cntrl" % i)
+        
         #
         # Add controllers and sequencers to the appropriate lists
         #
@@ -109,9 +113,11 @@
         l2_cntrl = L2Cache_Controller(version = i,
                                       L2cacheMemory = l2_cache)
         
+        exec("system.l2_cntrl%d = l2_cntrl" % i)
         l2_cntrl_nodes.append(l2_cntrl)
         
-    phys_mem_size = long(phys_mem.range.second) - long(phys_mem.range.first) + 
1
+    phys_mem_size = long(system.physmem.range.second) - \
+                      long(system.physmem.range.first) + 1
     mem_module_size = phys_mem_size / options.num_dirs
 
     for i in xrange(options.num_dirs):
@@ -127,9 +133,11 @@
         dir_cntrl = Directory_Controller(version = i,
                                          directory = \
                                          RubyDirectoryMemory(version = i,
-                                                             size = dir_size),
+                                                             size = \
+                                                               dir_size),
                                          memBuffer = mem_cntrl)
 
+        exec("system.dir_cntrl%d = dir_cntrl" % i)
         dir_cntrl_nodes.append(dir_cntrl)
 
     for i, dma_device in enumerate(dma_devices):
@@ -137,13 +145,14 @@
         # Create the Ruby objects associated with the dma controller
         #
         dma_seq = DMASequencer(version = i,
-                               physMemPort = phys_mem.port,
-                               physmem = phys_mem)
+                               physMemPort = system.physmem.port,
+                               physmem = system.physmem)
         
         dma_cntrl = DMA_Controller(version = i,
                                    dma_sequencer = dma_seq)
 
         dma_cntrl.dma_sequencer.port = dma_device.dma
+        exec("system.dma_cntrl%d = dma_cntrl" % i)
         dma_cntrl_nodes.append(dma_cntrl)
 
     all_cntrls = l1_cntrl_nodes + \
diff -r 86c3bf056a0d -r 1e1f63dfd130 configs/ruby/MI_example.py
--- a/configs/ruby/MI_example.py        Fri Aug 20 11:46:11 2010 -0700
+++ b/configs/ruby/MI_example.py        Fri Aug 20 11:46:11 2010 -0700
@@ -40,7 +40,7 @@
 def define_options(parser):
     return
 
-def create_system(options, phys_mem, piobus, dma_devices):
+def create_system(options, system, piobus, dma_devices):
     
     if buildEnv['PROTOCOL'] != 'MI_example':
         panic("This script requires the MI_example protocol to be built.")
@@ -76,8 +76,8 @@
         cpu_seq = RubySequencer(version = i,
                                 icache = cache,
                                 dcache = cache,
-                                physMemPort = phys_mem.port,
-                                physmem = phys_mem)
+                                physMemPort = system.physmem.port,
+                                physmem = system.physmem)
 
         if piobus != None:
             cpu_seq.pio_port = piobus.port
@@ -85,13 +85,16 @@
         l1_cntrl = L1Cache_Controller(version = i,
                                       sequencer = cpu_seq,
                                       cacheMemory = cache)
+
+        exec("system.l1_cntrl%d = l1_cntrl" % i)
         #
         # Add controllers and sequencers to the appropriate lists
         #
         cpu_sequencers.append(cpu_seq)
         l1_cntrl_nodes.append(l1_cntrl)
 
-    phys_mem_size = long(phys_mem.range.second) - long(phys_mem.range.first) + 
1
+    phys_mem_size = long(system.physmem.range.second) - \
+                      long(system.physmem.range.first) + 1
     mem_module_size = phys_mem_size / options.num_dirs
 
     for i in xrange(options.num_dirs):
@@ -106,12 +109,15 @@
 
         dir_cntrl = Directory_Controller(version = i,
                                          directory = \
-                                         RubyDirectoryMemory(version = i,
-                                               size = dir_size,
-                                               use_map = options.use_map,
-                                               map_levels = 
options.map_levels),
+                                         RubyDirectoryMemory( \
+                                                    version = i,
+                                                    size = dir_size,
+                                                    use_map = options.use_map,
+                                                    map_levels = \
+                                                      options.map_levels),
                                          memBuffer = mem_cntrl)
 
+        exec("system.dir_cntrl%d = dir_cntrl" % i)
         dir_cntrl_nodes.append(dir_cntrl)
 
     for i, dma_device in enumerate(dma_devices):
@@ -119,12 +125,13 @@
         # Create the Ruby objects associated with the dma controller
         #
         dma_seq = DMASequencer(version = i,
-                               physMemPort = phys_mem.port,
-                               physmem = phys_mem)
+                               physMemPort = system.physmem.port,
+                               physmem = system.physmem)
         
         dma_cntrl = DMA_Controller(version = i,
                                    dma_sequencer = dma_seq)
 
+        exec("system.dma_cntrl%d = dma_cntrl" % i)
         dma_cntrl.dma_sequencer.port = dma_device.dma
         dma_cntrl_nodes.append(dma_cntrl)
 
diff -r 86c3bf056a0d -r 1e1f63dfd130 configs/ruby/MOESI_CMP_directory.py
--- a/configs/ruby/MOESI_CMP_directory.py       Fri Aug 20 11:46:11 2010 -0700
+++ b/configs/ruby/MOESI_CMP_directory.py       Fri Aug 20 11:46:11 2010 -0700
@@ -47,7 +47,7 @@
 def define_options(parser):
     return
 
-def create_system(options, phys_mem, piobus, dma_devices):
+def create_system(options, system, piobus, dma_devices):
     
     if buildEnv['PROTOCOL'] != 'MOESI_CMP_directory':
         panic("This script requires the MOESI_CMP_directory protocol to be 
built.")
@@ -81,8 +81,8 @@
         cpu_seq = RubySequencer(version = i,
                                 icache = l1i_cache,
                                 dcache = l1d_cache,
-                                physMemPort = phys_mem.port,
-                                physmem = phys_mem)
+                                physMemPort = system.physmem.port,
+                                physmem = system.physmem)
 
         if piobus != None:
             cpu_seq.pio_port = piobus.port
@@ -92,7 +92,10 @@
                                       L1IcacheMemory = l1i_cache,
                                       L1DcacheMemory = l1d_cache,
                                       l2_select_num_bits = \
-                                        math.log(options.num_l2caches, 2))
+                                      math.log(options.num_l2caches,
+                                               2))
+
+        exec("system.l1_cntrl%d = l1_cntrl" % i)
         #
         # Add controllers and sequencers to the appropriate lists
         #
@@ -109,9 +112,11 @@
         l2_cntrl = L2Cache_Controller(version = i,
                                       L2cacheMemory = l2_cache)
         
+        exec("system.l2_cntrl%d = l2_cntrl" % i)
         l2_cntrl_nodes.append(l2_cntrl)
         
-    phys_mem_size = long(phys_mem.range.second) - long(phys_mem.range.first) + 
1
+    phys_mem_size = long(system.physmem.range.second) - \
+                      long(system.physmem.range.first) + 1
     mem_module_size = phys_mem_size / options.num_dirs
 
     for i in xrange(options.num_dirs):
@@ -127,9 +132,11 @@
         dir_cntrl = Directory_Controller(version = i,
                                          directory = \
                                          RubyDirectoryMemory(version = i,
-                                                             size = dir_size),
+                                                             size = \
+                                                             dir_size),
                                          memBuffer = mem_cntrl)
 
+        exec("system.dir_cntrl%d = dir_cntrl" % i)
         dir_cntrl_nodes.append(dir_cntrl)
 
     for i, dma_device in enumerate(dma_devices):
@@ -137,12 +144,13 @@
         # Create the Ruby objects associated with the dma controller
         #
         dma_seq = DMASequencer(version = i,
-                               physMemPort = phys_mem.port,
-                               physmem = phys_mem)
+                               physMemPort = system.physmem.port,
+                               physmem = system.physmem)
         
         dma_cntrl = DMA_Controller(version = i,
                                    dma_sequencer = dma_seq)
 
+        exec("system.dma_cntrl%d = dma_cntrl" % i)
         dma_cntrl.dma_sequencer.port = dma_device.dma
         dma_cntrl_nodes.append(dma_cntrl)
 
diff -r 86c3bf056a0d -r 1e1f63dfd130 configs/ruby/MOESI_CMP_token.py
--- a/configs/ruby/MOESI_CMP_token.py   Fri Aug 20 11:46:11 2010 -0700
+++ b/configs/ruby/MOESI_CMP_token.py   Fri Aug 20 11:46:11 2010 -0700
@@ -52,7 +52,7 @@
     parser.add_option("--disable-dyn-timeouts", action="store_true",
           help="Token_CMP: disable dyanimc timeouts, use fixed latency 
instead")
 
-def create_system(options, phys_mem, piobus, dma_devices):
+def create_system(options, system, piobus, dma_devices):
     
     if buildEnv['PROTOCOL'] != 'MOESI_CMP_token':
         panic("This script requires the MOESI_CMP_token protocol to be built.")
@@ -92,8 +92,8 @@
         cpu_seq = RubySequencer(version = i,
                                 icache = l1i_cache,
                                 dcache = l1d_cache,
-                                physMemPort = phys_mem.port,
-                                physmem = phys_mem)
+                                physMemPort = system.physmem.port,
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