changeset 84e8f914b3b8 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=84e8f914b3b8
description:
ruby: Reincarnated the responding machine profiling
This patch adds back to ruby the capability to understand the response
time
for messages that hit in different levels of the cache heirarchy.
Specifically add support for the MI_example, MOESI_hammer, and
MOESI_CMP_token
protocols.
diffstat:
src/mem/protocol/MI_example-cache.sm | 40 ++++++++++++-
src/mem/protocol/MOESI_CMP_token-L1cache.sm | 66 +++++++++++++---------
src/mem/protocol/MOESI_hammer-cache.sm | 83 ++++++++++++++++++++++++++--
src/mem/protocol/RubySlicc_Types.sm | 2 +
src/mem/ruby/profiler/Profiler.cc | 22 ++++---
src/mem/ruby/profiler/Profiler.hh | 12 +++-
src/mem/ruby/system/Sequencer.cc | 26 +++++++-
src/mem/ruby/system/Sequencer.hh | 14 ++++-
8 files changed, 210 insertions(+), 55 deletions(-)
diffs (truncated from 529 to 300 lines):
diff -r 3d5d3653eaa4 -r 84e8f914b3b8 src/mem/protocol/MI_example-cache.sm
--- a/src/mem/protocol/MI_example-cache.sm Fri Aug 20 11:46:12 2010 -0700
+++ b/src/mem/protocol/MI_example-cache.sm Fri Aug 20 11:46:12 2010 -0700
@@ -121,6 +121,17 @@
}
}
+ GenericMachineType getNondirectHitMachType(MachineID sender) {
+ if (machineIDToMachineType(sender) == MachineType:L1Cache) {
+ //
+ // NOTE direct local hits should not call this
+ //
+ return GenericMachineType:L1Cache_wCC;
+ } else {
+ return ConvertMachToGenericMach(machineIDToMachineType(sender));
+ }
+ }
+
// NETWORK PORTS
@@ -263,14 +274,35 @@
action(r_load_hit, "r", desc="Notify sequencer the load completed.") {
DEBUG_EXPR(getCacheEntry(address).DataBlk);
- sequencer.readCallback(address, getCacheEntry(address).DataBlk);
+ sequencer.readCallback(address,
+ GenericMachineType:L1Cache,
+ getCacheEntry(address).DataBlk);
+ }
+
+ action(rx_load_hit, "rx", desc="External load completed.") {
+ peek(responseNetwork_in, ResponseMsg) {
+ DEBUG_EXPR(getCacheEntry(address).DataBlk);
+ sequencer.readCallback(address,
+ getNondirectHitMachType(in_msg.Sender),
+ getCacheEntry(address).DataBlk);
+ }
}
action(s_store_hit, "s", desc="Notify sequencer that store completed.") {
DEBUG_EXPR(getCacheEntry(address).DataBlk);
- sequencer.writeCallback(address, getCacheEntry(address).DataBlk);
+ sequencer.writeCallback(address,
+ GenericMachineType:L1Cache,
+ getCacheEntry(address).DataBlk);
}
+ action(sx_store_hit, "sx", desc="External store completed.") {
+ peek(responseNetwork_in, ResponseMsg) {
+ DEBUG_EXPR(getCacheEntry(address).DataBlk);
+ sequencer.writeCallback(address,
+ getNondirectHitMachType(in_msg.Sender),
+ getCacheEntry(address).DataBlk);
+ }
+ }
action(u_writeDataToCache, "u", desc="Write data to the cache") {
peek(responseNetwork_in, ResponseMsg) {
@@ -342,14 +374,14 @@
transition(IS, Data, M) {
u_writeDataToCache;
- r_load_hit;
+ rx_load_hit;
w_deallocateTBE;
n_popResponseQueue;
}
transition(IM, Data, M) {
u_writeDataToCache;
- s_store_hit;
+ sx_store_hit;
w_deallocateTBE;
n_popResponseQueue;
}
diff -r 3d5d3653eaa4 -r 84e8f914b3b8 src/mem/protocol/MOESI_CMP_token-L1cache.sm
--- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm Fri Aug 20 11:46:12
2010 -0700
+++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm Fri Aug 20 11:46:12
2010 -0700
@@ -374,24 +374,27 @@
}
}
-// GenericMachineType getNondirectHitMachType(Address addr, MachineID sender)
{
-// if (machineIDToMachineType(sender) == MachineType:L1Cache) {
-// return GenericMachineType:L1Cache_wCC; // NOTE direct L1 hits should
not call this
-// } else if (machineIDToMachineType(sender) == MachineType:L2Cache) {
-//
-// if (sender == (mapAddressToRange(addr,
-// MachineType:L2Cache,
-// l2_select_low_bit,
-// l2_select_num_bits))) {
-//
-// return GenericMachineType:L2Cache;
-// } else {
-// return GenericMachineType:L2Cache_wCC;
-// }
-// } else {
-// return ConvertMachToGenericMach(machineIDToMachineType(sender));
-// }
-// }
+ GenericMachineType getNondirectHitMachType(Address addr, MachineID sender) {
+ if (machineIDToMachineType(sender) == MachineType:L1Cache) {
+ //
+ // NOTE direct local hits should not call this
+ //
+ return GenericMachineType:L1Cache_wCC;
+ } else if (machineIDToMachineType(sender) == MachineType:L2Cache) {
+
+ if (sender == (mapAddressToRange(addr,
+ MachineType:L2Cache,
+ l2_select_low_bit,
+ l2_select_num_bits))) {
+
+ return GenericMachineType:L2Cache;
+ } else {
+ return GenericMachineType:L2Cache_wCC;
+ }
+ } else {
+ return ConvertMachToGenericMach(machineIDToMachineType(sender));
+ }
+ }
bool okToIssueStarving(Address addr, MachineID machinID) {
return persistentTable.okToIssueStarving(addr, machineID);
@@ -1136,8 +1139,11 @@
action(h_load_hit, "h", desc="Notify sequencer the load completed.") {
DEBUG_EXPR(address);
DEBUG_EXPR(getCacheEntry(address).DataBlk);
- //sequencer.readCallback(address, getCacheEntry(address).DataBlk,
GenericMachineType:L1Cache, PrefetchBit:No);
- sequencer.readCallback(address, getCacheEntry(address).DataBlk);
+
+ sequencer.readCallback(address,
+ GenericMachineType:L1Cache,
+ getCacheEntry(address).DataBlk);
+
}
action(x_external_load_hit, "x", desc="Notify sequencer the load
completed.") {
@@ -1145,16 +1151,21 @@
DEBUG_EXPR(getCacheEntry(address).DataBlk);
peek(responseNetwork_in, ResponseMsg) {
- //sequencer.readCallback(address, getCacheEntry(address).DataBlk,
getNondirectHitMachType(in_msg.Address, in_msg.Sender), PrefetchBit:No);
- sequencer.readCallback(address, getCacheEntry(address).DataBlk);
+ sequencer.readCallback(address,
+ getNondirectHitMachType(address, in_msg.Sender),
+ getCacheEntry(address).DataBlk);
+
}
}
action(hh_store_hit, "\h", desc="Notify sequencer that store completed.") {
DEBUG_EXPR(address);
DEBUG_EXPR(getCacheEntry(address).DataBlk);
- //sequencer.writeCallback(address, getCacheEntry(address).DataBlk,
GenericMachineType:L1Cache, PrefetchBit:No);
- sequencer.writeCallback(address, getCacheEntry(address).DataBlk);
+
+ sequencer.writeCallback(address,
+ GenericMachineType:L1Cache,
+ getCacheEntry(address).DataBlk);
+
getCacheEntry(address).Dirty := true;
DEBUG_EXPR(getCacheEntry(address).DataBlk);
}
@@ -1163,8 +1174,11 @@
DEBUG_EXPR(address);
DEBUG_EXPR(getCacheEntry(address).DataBlk);
peek(responseNetwork_in, ResponseMsg) {
- //sequencer.writeCallback(address, getCacheEntry(address).DataBlk,
getNondirectHitMachType(in_msg.Address, in_msg.Sender), PrefetchBit:No);
- sequencer.writeCallback(address, getCacheEntry(address).DataBlk);
+
+ sequencer.writeCallback(address,
+ getNondirectHitMachType(address, in_msg.Sender),
+ getCacheEntry(address).DataBlk);
+
}
getCacheEntry(address).Dirty := true;
DEBUG_EXPR(getCacheEntry(address).DataBlk);
diff -r 3d5d3653eaa4 -r 84e8f914b3b8 src/mem/protocol/MOESI_hammer-cache.sm
--- a/src/mem/protocol/MOESI_hammer-cache.sm Fri Aug 20 11:46:12 2010 -0700
+++ b/src/mem/protocol/MOESI_hammer-cache.sm Fri Aug 20 11:46:12 2010 -0700
@@ -114,6 +114,7 @@
State CacheState, desc="cache state";
bool Dirty, desc="Is the data dirty (different than memory)?";
DataBlock DataBlk, desc="data for the block";
+ bool FromL2, default="false", desc="block just moved from L2";
}
// TBE fields
@@ -123,6 +124,7 @@
bool Dirty, desc="Is the data dirty (different than memory)?";
int NumPendingMsgs, desc="Number of acks/data messages that this
processor is waiting for";
bool Sharers, desc="On a GetS, did we find any other sharers in
the system";
+ MachineID LastResponder, desc="last machine to send a response for this
request";
}
external_type(TBETable) {
@@ -214,6 +216,26 @@
}
}
+ GenericMachineType getNondirectHitMachType(Address addr, MachineID sender) {
+ if (machineIDToMachineType(sender) == MachineType:L1Cache) {
+ //
+ // NOTE direct local hits should not call this
+ //
+ return GenericMachineType:L1Cache_wCC;
+ } else {
+ return ConvertMachToGenericMach(machineIDToMachineType(sender));
+ }
+ }
+
+ GenericMachineType testAndClearLocalHit(Address addr) {
+ if (getCacheEntry(addr).FromL2) {
+ getCacheEntry(addr).FromL2 := false;
+ return GenericMachineType:L2Cache;
+ } else {
+ return GenericMachineType:L1Cache;
+ }
+ }
+
MessageBuffer triggerQueue, ordered="true";
// ** OUT_PORTS **
@@ -487,12 +509,54 @@
action(h_load_hit, "h", desc="Notify sequencer the load completed.") {
DEBUG_EXPR(getCacheEntry(address).DataBlk);
- sequencer.readCallback(address, getCacheEntry(address).DataBlk);
+
+ sequencer.readCallback(address,
+ testAndClearLocalHit(address),
+ getCacheEntry(address).DataBlk);
+
+ }
+
+ action(hx_external_load_hit, "hx", desc="load required external msgs") {
+ DEBUG_EXPR(getCacheEntry(address).DataBlk);
+ peek(responseToCache_in, ResponseMsg) {
+
+ sequencer.readCallback(address,
+ getNondirectHitMachType(in_msg.Address,
in_msg.Sender),
+ getCacheEntry(address).DataBlk);
+
+ }
}
action(hh_store_hit, "\h", desc="Notify sequencer that store completed.") {
DEBUG_EXPR(getCacheEntry(address).DataBlk);
- sequencer.writeCallback(address, getCacheEntry(address).DataBlk);
+
+ sequencer.writeCallback(address,
+ testAndClearLocalHit(address),
+ getCacheEntry(address).DataBlk);
+
+ getCacheEntry(address).Dirty := true;
+ }
+
+ action(sx_external_store_hit, "sx", desc="store required external msgs.") {
+ DEBUG_EXPR(getCacheEntry(address).DataBlk);
+ peek(responseToCache_in, ResponseMsg) {
+
+ sequencer.writeCallback(address,
+ getNondirectHitMachType(address, in_msg.Sender),
+ getCacheEntry(address).DataBlk);
+
+ }
+ getCacheEntry(address).Dirty := true;
+ }
+
+ action(sxt_trig_ext_store_hit, "sxt", desc="store required external msgs.") {
+ DEBUG_EXPR(getCacheEntry(address).DataBlk);
+
+ sequencer.writeCallback(address,
+ getNondirectHitMachType(address,
+
TBEs[address].LastResponder),
+ getCacheEntry(address).DataBlk);
+
getCacheEntry(address).Dirty := true;
}
@@ -522,6 +586,7 @@
DEBUG_EXPR(TBEs[address].NumPendingMsgs);
TBEs[address].NumPendingMsgs := TBEs[address].NumPendingMsgs -
in_msg.Acks;
DEBUG_EXPR(TBEs[address].NumPendingMsgs);
+ TBEs[address].LastResponder := in_msg.Sender;
}
}
@@ -671,9 +736,11 @@
if (L1DcacheMemory.isTagPresent(address)) {
static_cast(Entry, L1DcacheMemory[address]).Dirty := static_cast(Entry,
L2cacheMemory[address]).Dirty;
static_cast(Entry, L1DcacheMemory[address]).DataBlk :=
static_cast(Entry, L2cacheMemory[address]).DataBlk;
+ static_cast(Entry, L1DcacheMemory[address]).FromL2 := true;
} else {
static_cast(Entry, L1IcacheMemory[address]).Dirty := static_cast(Entry,
L2cacheMemory[address]).Dirty;
static_cast(Entry, L1IcacheMemory[address]).DataBlk :=
static_cast(Entry, L2cacheMemory[address]).DataBlk;
+ static_cast(Entry, L1IcacheMemory[address]).FromL2 := true;
}
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