changeset b10ee98aea91 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=b10ee98aea91
description:
ruby: Reduced ruby latencies
The previous slower ruby latencies created a mismatch between the
faster M5
cpu models and the much slower ruby memory system. Specifically smp
interrupts were much slower and infrequent, as well as cpus moving in
and out
of spin locks. The result was many cpus were idle for large periods of
time.
These changes fix the latency mismatch.
diffstat:
configs/common/Options.py | 2 +-
configs/example/ruby_se.py | 2 +-
configs/ruby/MOESI_CMP_token.py | 4 ++--
configs/ruby/MOESI_hammer.py | 4 ++--
src/mem/protocol/MOESI_CMP_token-L1cache.sm | 2 +-
src/mem/protocol/MOESI_CMP_token-L2cache.sm | 4 ++--
src/mem/protocol/MOESI_CMP_token-dir.sm | 4 ++--
src/mem/protocol/MOESI_hammer-cache.sm | 2 +-
src/mem/protocol/MOESI_hammer-dir.sm | 2 +-
9 files changed, 13 insertions(+), 13 deletions(-)
diffs (127 lines):
diff -r 7d97cec15818 -r b10ee98aea91 configs/common/Options.py
--- a/configs/common/Options.py Fri Aug 20 11:46:12 2010 -0700
+++ b/configs/common/Options.py Fri Aug 20 11:46:12 2010 -0700
@@ -34,7 +34,7 @@
parser.add_option("--caches", action="store_true")
parser.add_option("--l2cache", action="store_true")
parser.add_option("--fastmem", action="store_true")
-parser.add_option("--clock", action="store", type="string", default='1GHz')
+parser.add_option("--clock", action="store", type="string", default='2GHz')
parser.add_option("--num-dirs", type="int", default=1)
parser.add_option("--num-l2caches", type="int", default=1)
parser.add_option("--num-l3caches", type="int", default=1)
diff -r 7d97cec15818 -r b10ee98aea91 configs/example/ruby_se.py
--- a/configs/example/ruby_se.py Fri Aug 20 11:46:12 2010 -0700
+++ b/configs/example/ruby_se.py Fri Aug 20 11:46:12 2010 -0700
@@ -143,7 +143,7 @@
assert(test_mem_mode == 'timing')
assert(FutureClass == None)
-CPUClass.clock = '1GHz'
+CPUClass.clock = options.clock
np = options.num_cpus
diff -r 7d97cec15818 -r b10ee98aea91 configs/ruby/MOESI_CMP_token.py
--- a/configs/ruby/MOESI_CMP_token.py Fri Aug 20 11:46:12 2010 -0700
+++ b/configs/ruby/MOESI_CMP_token.py Fri Aug 20 11:46:12 2010 -0700
@@ -36,13 +36,13 @@
# Note: the L1 Cache latency is only used by the sequencer on fast path hits
#
class L1Cache(RubyCache):
- latency = 3
+ latency = 2
#
# Note: the L2 Cache latency is not currently used
#
class L2Cache(RubyCache):
- latency = 15
+ latency = 10
def define_options(parser):
parser.add_option("--l1-retries", type="int", default=1,
diff -r 7d97cec15818 -r b10ee98aea91 configs/ruby/MOESI_hammer.py
--- a/configs/ruby/MOESI_hammer.py Fri Aug 20 11:46:12 2010 -0700
+++ b/configs/ruby/MOESI_hammer.py Fri Aug 20 11:46:12 2010 -0700
@@ -35,13 +35,13 @@
# Note: the L1 Cache latency is only used by the sequencer on fast path hits
#
class L1Cache(RubyCache):
- latency = 3
+ latency = 2
#
# Note: the L2 Cache latency is not currently used
#
class L2Cache(RubyCache):
- latency = 15
+ latency = 10
def define_options(parser):
return
diff -r 7d97cec15818 -r b10ee98aea91 src/mem/protocol/MOESI_CMP_token-L1cache.sm
--- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm Fri Aug 20 11:46:12
2010 -0700
+++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm Fri Aug 20 11:46:12
2010 -0700
@@ -41,7 +41,7 @@
int l1_request_latency = 2,
int l1_response_latency = 2,
int retry_threshold = 1,
- int fixed_timeout_latency = 300,
+ int fixed_timeout_latency = 100,
bool dynamic_timeout_enabled = true
{
diff -r 7d97cec15818 -r b10ee98aea91 src/mem/protocol/MOESI_CMP_token-L2cache.sm
--- a/src/mem/protocol/MOESI_CMP_token-L2cache.sm Fri Aug 20 11:46:12
2010 -0700
+++ b/src/mem/protocol/MOESI_CMP_token-L2cache.sm Fri Aug 20 11:46:12
2010 -0700
@@ -35,8 +35,8 @@
machine(L2Cache, "Token protocol")
: CacheMemory * L2cacheMemory,
int N_tokens,
- int l2_request_latency = 10,
- int l2_response_latency = 10,
+ int l2_request_latency = 5,
+ int l2_response_latency = 5,
bool filtering_enabled = true
{
diff -r 7d97cec15818 -r b10ee98aea91 src/mem/protocol/MOESI_CMP_token-dir.sm
--- a/src/mem/protocol/MOESI_CMP_token-dir.sm Fri Aug 20 11:46:12 2010 -0700
+++ b/src/mem/protocol/MOESI_CMP_token-dir.sm Fri Aug 20 11:46:12 2010 -0700
@@ -36,9 +36,9 @@
: DirectoryMemory * directory,
MemoryControl * memBuffer,
int l2_select_num_bits,
- int directory_latency = 6,
+ int directory_latency = 5,
bool distributed_persistent = true,
- int fixed_timeout_latency = 300
+ int fixed_timeout_latency = 100
{
MessageBuffer dmaResponseFromDir, network="To", virtual_network="5",
ordered="true";
diff -r 7d97cec15818 -r b10ee98aea91 src/mem/protocol/MOESI_hammer-cache.sm
--- a/src/mem/protocol/MOESI_hammer-cache.sm Fri Aug 20 11:46:12 2010 -0700
+++ b/src/mem/protocol/MOESI_hammer-cache.sm Fri Aug 20 11:46:12 2010 -0700
@@ -38,7 +38,7 @@
CacheMemory * L1IcacheMemory,
CacheMemory * L1DcacheMemory,
CacheMemory * L2cacheMemory,
- int cache_response_latency = 12,
+ int cache_response_latency = 10,
int issue_latency = 2
{
diff -r 7d97cec15818 -r b10ee98aea91 src/mem/protocol/MOESI_hammer-dir.sm
--- a/src/mem/protocol/MOESI_hammer-dir.sm Fri Aug 20 11:46:12 2010 -0700
+++ b/src/mem/protocol/MOESI_hammer-dir.sm Fri Aug 20 11:46:12 2010 -0700
@@ -36,7 +36,7 @@
machine(Directory, "AMD Hammer-like protocol")
: DirectoryMemory * directory,
MemoryControl * memBuffer,
- int memory_controller_latency = 12
+ int memory_controller_latency = 2
{
MessageBuffer forwardFromDir, network="To", virtual_network="3",
ordered="false";
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