changeset f895258c9121 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=f895258c9121
description:
ruby: Fixed minor bug in ruby test for setting the request type
diffstat:
src/cpu/rubytest/Check.cc | 16 ++++++++--------
1 files changed, 8 insertions(+), 8 deletions(-)
diffs (45 lines):
diff -r 238f99c9f441 -r f895258c9121 src/cpu/rubytest/Check.cc
--- a/src/cpu/rubytest/Check.cc Fri Aug 20 11:46:14 2010 -0700
+++ b/src/cpu/rubytest/Check.cc Fri Aug 20 11:46:14 2010 -0700
@@ -82,10 +82,6 @@
Request::Flags flags;
flags.set(Request::PREFETCH);
- // Prefetches are assumed to be 0 sized
- Request *req = new Request(m_address.getAddress(), 0, flags, curTick,
- m_pc.getAddress());
-
Packet::Command cmd;
// 1 in 8 chance this will be an exclusive prefetch
@@ -101,6 +97,10 @@
flags.set(Request::PF_EXCLUSIVE);
}
+ // Prefetches are assumed to be 0 sized
+ Request *req = new Request(m_address.getAddress(), 0, flags, curTick,
+ m_pc.getAddress());
+
PacketPtr pkt = new Packet(req, cmd, port->idx);
// push the subblock onto the sender state. The sequencer will
@@ -198,15 +198,15 @@
Request::Flags flags;
- // Checks are sized depending on the number of bytes written
- Request *req = new Request(m_address.getAddress(), CHECK_SIZE, flags,
- curTick, m_pc.getAddress());
-
// 50% chance that the request will be an instruction fetch
if ((random() & 0x1) == 0) {
flags.set(Request::INST_FETCH);
}
+ // Checks are sized depending on the number of bytes written
+ Request *req = new Request(m_address.getAddress(), CHECK_SIZE, flags,
+ curTick, m_pc.getAddress());
+
PacketPtr pkt = new Packet(req, MemCmd::ReadReq, port->idx);
uint8_t* dataArray = new uint8_t[CHECK_SIZE];
pkt->dataDynamicArray(dataArray);
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