changeset 27dbb92bbad5 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=27dbb92bbad5
description:
ARM: Clean up the ISA desc portion of the ARM memory instructions.
diffstat:
src/arch/arm/isa/insts/ldr.isa | 522 ++++++++++++++++++-------------------
src/arch/arm/isa/insts/mem.isa | 146 ++--------
src/arch/arm/isa/insts/str.isa | 543 ++++++++++++++++++++-------------------
src/arch/arm/isa/insts/swap.isa | 63 +++-
4 files changed, 605 insertions(+), 669 deletions(-)
diffs (truncated from 1382 to 300 lines):
diff -r 361b287b94b6 -r 27dbb92bbad5 src/arch/arm/isa/insts/ldr.isa
--- a/src/arch/arm/isa/insts/ldr.isa Mon Aug 23 11:18:40 2010 -0500
+++ b/src/arch/arm/isa/insts/ldr.isa Mon Aug 23 11:18:40 2010 -0500
@@ -43,285 +43,265 @@
decoder_output = ""
exec_output = ""
- def loadImmClassName(post, add, writeback, \
- size=4, sign=False, user=False):
- return memClassName("LOAD_IMM", post, add, writeback,
- size, sign, user)
+ class LoadInst(LoadStoreInst):
+ execBase = 'Load'
- def loadRegClassName(post, add, writeback, \
- size=4, sign=False, user=False):
- return memClassName("LOAD_REG", post, add, writeback,
- size, sign, user)
+ def __init__(self, mnem, post, add, writeback,
+ size=4, sign=False, user=False, flavor="normal"):
+ super(LoadInst, self).__init__()
+
+ self.name = mnem
+ self.post = post
+ self.add = add
+ self.writeback = writeback
+ self.size = size
+ self.sign = sign
+ self.user = user
+ self.flavor = flavor
+
+ if self.add:
+ self.op = " +"
+ else:
+ self.op = " -"
+
+ self.memFlags = ["ArmISA::TLB::MustBeOne"]
+ self.codeBlobs = {"postacc_code" : ""}
+
+ def emitHelper(self, base = 'Memory'):
+
+ global header_output, decoder_output, exec_output
+
+ codeBlobs = self.codeBlobs
+ codeBlobs["predicate_test"] = pickPredicate(codeBlobs)
+ (newHeader,
+ newDecoder,
+ newExec) = self.fillTemplates(self.name, self.Name, codeBlobs,
+ self.memFlags, [], base)
+
+ header_output += newHeader
+ decoder_output += newDecoder
+ exec_output += newExec
+
+ class RfeInst(LoadInst):
+ decConstBase = 'Rfe'
+
+ def __init__(self, mnem, post, add, writeback):
+ super(RfeInst, self).__init__(mnem, post, add, writeback)
+ self.Name = "RFE_" + loadImmClassName(post, add, writeback, 8)
+
+ self.memFlags.append("ArmISA::TLB::AlignWord")
+
+ def emit(self):
+ offset = 0
+ if self.post != self.add:
+ offset += 4
+ if not self.add:
+ offset -= 8
+ self.codeBlobs["ea_code"] = "EA = Base + %d;" % offset
+
+ wbDiff = -8
+ if self.add:
+ wbDiff = 8
+ accCode = '''
+ CPSR cpsr = Cpsr;
+ SCTLR sctlr = Sctlr;
+ NPC = cSwap<uint32_t>(Mem.ud, cpsr.e);
+ uint32_t newCpsr =
+ cpsrWriteByInstr(cpsr | CondCodes,
+ cSwap<uint32_t>(Mem.ud >> 32, cpsr.e),
+ 0xF, true, sctlr.nmfi);
+ Cpsr = ~CondCodesMask & newCpsr;
+ CondCodes = CondCodesMask & newCpsr;
+ '''
+ if self.writeback:
+ accCode += "Base = Base + %s;\n" % wbDiff
+ self.codeBlobs["memacc_code"] = accCode
+
+ self.emitHelper('RfeOp')
+
+ class LoadImmInst(LoadInst):
+ def __init__(self, *args, **kargs):
+ super(LoadImmInst, self).__init__(*args, **kargs)
+ self.offset = self.op + " imm"
+
+ class LoadRegInst(LoadInst):
+ def __init__(self, *args, **kargs):
+ super(LoadRegInst, self).__init__(*args, **kargs)
+ self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \
+ " shiftType, CondCodes<29:>)"
+
+ class LoadSingle(LoadInst):
+ def __init__(self, *args, **kargs):
+ super(LoadSingle, self).__init__(*args, **kargs)
+
+ # Build the default class name
+ self.Name = self.nameFunc(self.post, self.add, self.writeback,
+ self.size, self.sign, self.user)
+
+ # Add memory request flags where necessary
+ self.memFlags.append("%d" % (self.size - 1))
+ if self.user:
+ self.memFlags.append("ArmISA::TLB::UserMode")
+
+ if self.flavor == "prefetch":
+ self.memFlags.append("Request::PREFETCH")
+ elif self.flavor == "exclusive":
+ self.memFlags.append("Request::LLSC")
+ elif self.flavor == "normal":
+ self.memFlags.append("ArmISA::TLB::AllowUnaligned")
+
+ # Disambiguate the class name for different flavors of loads
+ if self.flavor != "normal":
+ self.Name = "%s_%s" % (self.name.upper(), self.Name)
+
+ def emit(self):
+ # Address compuation code
+ eaCode = "EA = Base"
+ if not self.post:
+ eaCode += self.offset
+ eaCode += ";"
+ self.codeBlobs["ea_code"] = eaCode
+
+ # Code that actually handles the access
+ if self.flavor == "prefetch":
+ accCode = 'uint64_t temp = Mem%s; temp = temp;'
+ elif self.flavor == "fp":
+ accCode = "FpDest.uw = cSwap(Mem%s, ((CPSR)Cpsr).e);\n"
+ else:
+ accCode = "IWDest = cSwap(Mem%s, ((CPSR)Cpsr).e);"
+ accCode = accCode % buildMemSuffix(self.sign, self.size)
+
+ if self.writeback:
+ accCode += "Base = Base %s;\n" % self.offset
+
+ self.codeBlobs["memacc_code"] = accCode
+
+ # Push it out to the output files
+ base = buildMemBase(self.basePrefix, self.post, self.writeback)
+ self.emitHelper(base)
+
+ def loadImmClassName(post, add, writeback, size=4, sign=False, user=False):
+ return memClassName("LOAD_IMM", post, add, writeback, size, sign, user)
+
+ class LoadImm(LoadImmInst, LoadSingle):
+ decConstBase = 'LoadStoreImm'
+ basePrefix = 'MemoryImm'
+ nameFunc = staticmethod(loadImmClassName)
+
+ def loadRegClassName(post, add, writeback, size=4, sign=False, user=False):
+ return memClassName("LOAD_REG", post, add, writeback, size, sign, user)
+
+ class LoadReg(LoadRegInst, LoadSingle):
+ decConstBase = 'LoadStoreReg'
+ basePrefix = 'MemoryReg'
+ nameFunc = staticmethod(loadRegClassName)
+
+ class LoadDouble(LoadInst):
+ def __init__(self, *args, **kargs):
+ super(LoadDouble, self).__init__(*args, **kargs)
+
+ # Build the default class name
+ self.Name = self.nameFunc(self.post, self.add, self.writeback)
+
+ # Add memory request flags where necessary
+ if self.flavor == "exclusive":
+ self.memFlags.append("Request::LLSC")
+ self.memFlags.append("ArmISA::TLB::AlignWord")
+
+ # Disambiguate the class name for different flavors of loads
+ if self.flavor != "normal":
+ self.Name = "%s_%s" % (self.name.upper(), self.Name)
+
+ def emit(self):
+ # Address computation code
+ eaCode = "EA = Base"
+ if not self.post:
+ eaCode += self.offset
+ eaCode += ";"
+ self.codeBlobs["ea_code"] = eaCode
+
+ # Code that actually handles the access
+ if self.flavor != "fp":
+ accCode = '''
+ CPSR cpsr = Cpsr;
+ Dest = cSwap<uint32_t>(Mem.ud, cpsr.e);
+ Dest2 = cSwap<uint32_t>(Mem.ud >> 32, cpsr.e);
+ '''
+ else:
+ accCode = '''
+ uint64_t swappedMem = cSwap(Mem.ud, ((CPSR)Cpsr).e);
+ FpDest.uw = (uint32_t)swappedMem;
+ FpDest2.uw = (uint32_t)(swappedMem >> 32);
+ '''
+
+ if self.writeback:
+ accCode += "Base = Base %s;\n" % self.offset
+
+ self.codeBlobs["memacc_code"] = accCode
+
+ # Push it out to the output files
+ base = buildMemBase(self.basePrefix, self.post, self.writeback)
+ self.emitHelper(base)
def loadDoubleImmClassName(post, add, writeback):
return memClassName("LOAD_IMMD", post, add, writeback, 4, False, False)
+ class LoadDoubleImm(LoadImmInst, LoadDouble):
+ decConstBase = 'LoadStoreDImm'
+ basePrefix = 'MemoryDImm'
+ nameFunc = staticmethod(loadDoubleImmClassName)
+
def loadDoubleRegClassName(post, add, writeback):
return memClassName("LOAD_REGD", post, add, writeback, 4, False, False)
- def emitLoad(name, Name, imm, eaCode, accCode, \
- memFlags, instFlags, base, double=False):
- global header_output, decoder_output, exec_output
-
- (newHeader,
- newDecoder,
- newExec) = loadStoreBase(name, Name, imm,
- eaCode, accCode, "",
- memFlags, instFlags, double, False,
- base, execTemplateBase = 'Load')
-
- header_output += newHeader
- decoder_output += newDecoder
- exec_output += newExec
-
- def buildImmLoad(mnem, post, add, writeback, \
- size=4, sign=False, user=False, \
- prefetch=False, ldrex=False, vldr=False):
- name = mnem
- Name = loadImmClassName(post, add, writeback, \
- size, sign, user)
-
- if add:
- op = " +"
- else:
- op = " -"
-
- offset = op + " imm"
- eaCode = "EA = Base"
- if not post:
- eaCode += offset
- eaCode += ";"
-
- memFlags = ["ArmISA::TLB::MustBeOne", "%d" % (size - 1)]
- if user:
- memFlags.append("ArmISA::TLB::UserMode")
-
- if prefetch:
- Name = "%s_%s" % (mnem.upper(), Name)
- memFlags.append("Request::PREFETCH")
- accCode = '''
- uint64_t temp = Mem%s;\n
- temp = temp;
- ''' % buildMemSuffix(sign, size)
- elif vldr:
- Name = "%s_%s" % (mnem.upper(), Name)
- accCode = "FpDest.uw = cSwap(Mem%s, ((CPSR)Cpsr).e);\n" % \
- buildMemSuffix(sign, size)
- else:
- if ldrex:
- memFlags.append("Request::LLSC")
- Name = "%s_%s" % (mnem.upper(), Name)
- accCode = "IWDest = cSwap(Mem%s, ((CPSR)Cpsr).e);" % \
- buildMemSuffix(sign, size)
-
- if not prefetch and not ldrex and not vldr:
- memFlags.append("ArmISA::TLB::AllowUnaligned")
-
- if writeback:
- accCode += "Base = Base %s;\n" % offset
- base = buildMemBase("MemoryImm", post, writeback)
-
- emitLoad(name, Name, True, eaCode, accCode, memFlags, [], base)
-
- def buildRfeLoad(mnem, post, add, writeback):
- name = mnem
- Name = "RFE_" + loadImmClassName(post, add, writeback, 8)
-
- offset = 0
- if post != add:
- offset += 4
- if not add:
- offset -= 8
-
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