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Review request for Default. Summary ------- ARM: Use less micro-ops for register update loads if possible. Allow some loads that update the base register to use just two micro-ops. three micro-ops are only used if the destination register matches the offset register or the PC is the destination register. If the PC is updated it needs to be the last micro-op otherwise O3 will mispredict. Diffs ----- src/arch/arm/insts/macromem.hh 47d9409b2b7f src/arch/arm/insts/macromem.cc 47d9409b2b7f src/arch/arm/insts/mem.hh 47d9409b2b7f src/arch/arm/isa/insts/ldr.isa 47d9409b2b7f src/arch/arm/isa/insts/macromem.isa 47d9409b2b7f src/arch/arm/isa/insts/mem.isa 47d9409b2b7f src/arch/arm/isa/insts/str.isa 47d9409b2b7f src/arch/arm/isa/templates/macromem.isa 47d9409b2b7f src/arch/arm/isa/templates/mem.isa 47d9409b2b7f src/arch/arm/isa/templates/pred.isa 47d9409b2b7f Diff: http://reviews.m5sim.org/r/225/diff Testing ------- Thanks, Ali _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
