changeset 3b0c4b819651 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=3b0c4b819651
description:
ISA: Get rid of old, unused utility functions cluttering up the ISAs.
diffstat:
src/arch/alpha/ev5.cc | 47 -------------------------
src/arch/alpha/utility.hh | 69 -------------------------------------
src/arch/arm/utility.hh | 19 ----------
src/arch/mips/mips_core_specific.cc | 5 --
src/arch/mips/mips_core_specific.hh | 7 ---
src/arch/mips/utility.hh | 24 ------------
src/arch/power/utility.hh | 27 --------------
src/arch/sparc/utility.hh | 38 --------------------
src/arch/x86/utility.hh | 38 --------------------
src/cpu/o3/fetch.hh | 1 -
src/cpu/ozone/front_end.hh | 1 -
11 files changed, 0 insertions(+), 276 deletions(-)
diffs (truncated from 391 to 300 lines):
diff -r bdd926760470 -r 3b0c4b819651 src/arch/alpha/ev5.cc
--- a/src/arch/alpha/ev5.cc Mon Aug 23 09:44:19 2010 -0700
+++ b/src/arch/alpha/ev5.cc Mon Aug 23 16:14:20 2010 -0700
@@ -66,53 +66,6 @@
delete reset;
}
-
-template <class CPU>
-void
-processInterrupts(CPU *cpu)
-{
- //Check if there are any outstanding interrupts
- //Handle the interrupts
- int ipl = 0;
- int summary = 0;
-
- if (cpu->readMiscRegNoEffect(IPR_ASTRR))
- panic("asynchronous traps not implemented\n");
-
- if (cpu->readMiscRegNoEffect(IPR_SIRR)) {
- for (int i = INTLEVEL_SOFTWARE_MIN;
- i < INTLEVEL_SOFTWARE_MAX; i++) {
- if (cpu->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) {
- // See table 4-19 of the 21164 hardware reference
- ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
- summary |= (ULL(1) << i);
- }
- }
- }
-
- uint64_t interrupts = cpu->intr_status();
-
- if (interrupts) {
- for (int i = INTLEVEL_EXTERNAL_MIN;
- i < INTLEVEL_EXTERNAL_MAX; i++) {
- if (interrupts & (ULL(1) << i)) {
- // See table 4-19 of the 21164 hardware reference
- ipl = i;
- summary |= (ULL(1) << i);
- }
- }
- }
-
- if (ipl && ipl > cpu->readMiscRegNoEffect(IPR_IPLR)) {
- cpu->setMiscRegNoEffect(IPR_ISR, summary);
- cpu->setMiscRegNoEffect(IPR_INTID, ipl);
- cpu->trap(new InterruptFault);
- DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
- cpu->readMiscRegNoEffect(IPR_IPLR), ipl, summary);
- }
-
-}
-
template <class CPU>
void
zeroRegisters(CPU *cpu)
diff -r bdd926760470 -r 3b0c4b819651 src/arch/alpha/utility.hh
--- a/src/arch/alpha/utility.hh Mon Aug 23 09:44:19 2010 -0700
+++ b/src/arch/alpha/utility.hh Mon Aug 23 16:14:20 2010 -0700
@@ -49,68 +49,6 @@
return (tc->readMiscRegNoEffect(IPR_DTB_CM) & 0x18) != 0;
}
-inline bool
-isCallerSaveIntegerRegister(unsigned int reg)
-{
- panic("register classification not implemented");
- return (reg >= 1 && reg <= 8) || (reg >= 22 && reg <= 25) || reg == 27;
-}
-
-inline bool
-isCalleeSaveIntegerRegister(unsigned int reg)
-{
- panic("register classification not implemented");
- return reg >= 9 && reg <= 15;
-}
-
-inline bool
-isCallerSaveFloatRegister(unsigned int reg)
-{
- panic("register classification not implemented");
- return false;
-}
-
-inline bool
-isCalleeSaveFloatRegister(unsigned int reg)
-{
- panic("register classification not implemented");
- return false;
-}
-
-inline Addr
-alignAddress(const Addr &addr, unsigned int nbytes)
-{
- return (addr & ~(nbytes - 1));
-}
-
-// Instruction address compression hooks
-inline Addr
-realPCToFetchPC(const Addr &addr)
-{
- return addr;
-}
-
-inline Addr
-fetchPCToRealPC(const Addr &addr)
-{
- return addr;
-}
-
-// the size of "fetched" instructions (not necessarily the size
-// of real instructions for PISA)
-inline size_t
-fetchInstSize()
-{
- return sizeof(MachInst);
-}
-
-inline MachInst
-makeRegisterCopy(int dest, int src)
-{
- panic("makeRegisterCopy not implemented");
- return 0;
-}
-
/**
* Function to insure ISA semantics about 0 registers.
* @param tc The thread context.
@@ -150,13 +88,6 @@
void initIPRs(ThreadContext *tc, int cpuId);
#if FULL_SYSTEM
void initCPU(ThreadContext *tc, int cpuId);
-
-/**
- * Function to check for and process any interrupts.
- * @param tc The thread context.
- */
-template <class TC>
-void processInterrupts(TC *tc);
#endif
void copyRegs(ThreadContext *src, ThreadContext *dest);
diff -r bdd926760470 -r 3b0c4b819651 src/arch/arm/utility.hh
--- a/src/arch/arm/utility.hh Mon Aug 23 09:44:19 2010 -0700
+++ b/src/arch/arm/utility.hh Mon Aug 23 16:14:20 2010 -0700
@@ -96,25 +96,6 @@
template <class TC>
void zeroRegisters(TC *tc);
- // Instruction address compression hooks
- static inline Addr realPCToFetchPC(const Addr &addr) {
- return addr;
- }
-
- static inline Addr fetchPCToRealPC(const Addr &addr) {
- return addr;
- }
-
- // the size of "fetched" instructions
- static inline size_t fetchInstSize() {
- return sizeof(MachInst);
- }
-
- static inline MachInst makeRegisterCopy(int dest, int src) {
- panic("makeRegisterCopy not implemented");
- return 0;
- }
-
inline void startupCPU(ThreadContext *tc, int cpuId)
{
tc->activate(0);
diff -r bdd926760470 -r 3b0c4b819651 src/arch/mips/mips_core_specific.cc
--- a/src/arch/mips/mips_core_specific.cc Mon Aug 23 09:44:19 2010 -0700
+++ b/src/arch/mips/mips_core_specific.cc Mon Aug 23 16:14:20 2010 -0700
@@ -43,9 +43,4 @@
MipsISA::initCPU(ThreadContext *tc, int cpuId)
{}
-template <class CPU>
-void
-MipsISA::processInterrupts(CPU *cpu)
-{}
-
#endif // FULL_SYSTEM || BARE_IRON
diff -r bdd926760470 -r 3b0c4b819651 src/arch/mips/mips_core_specific.hh
--- a/src/arch/mips/mips_core_specific.hh Mon Aug 23 09:44:19 2010 -0700
+++ b/src/arch/mips/mips_core_specific.hh Mon Aug 23 16:14:20 2010 -0700
@@ -37,13 +37,6 @@
namespace MipsISA {
void initCPU(ThreadContext *tc, int cpuId);
-
- /**
- * Function to check for and process any interrupts.
- * @param tc The thread context.
- */
- template <class CPU>
- void processInterrupts(CPU *cpu);
};
#endif // __ARCH_MIPS_CORE_SPECIFIC_HH__
diff -r bdd926760470 -r 3b0c4b819651 src/arch/mips/utility.hh
--- a/src/arch/mips/utility.hh Mon Aug 23 09:44:19 2010 -0700
+++ b/src/arch/mips/utility.hh Mon Aug 23 16:14:20 2010 -0700
@@ -79,30 +79,6 @@
}
}
-// Instruction address compression hooks
-static inline Addr realPCToFetchPC(const Addr &addr) {
- return addr;
-}
-
-static inline Addr fetchPCToRealPC(const Addr &addr) {
- return addr;
-}
-
-// the size of "fetched" instructions (not necessarily the size
-// of real instructions for PISA)
-static inline size_t fetchInstSize() {
- return sizeof(MachInst);
-}
-
-////////////////////////////////////////////////////////////////////////
-//
-// Register File Utility Functions
-//
-static inline MachInst makeRegisterCopy(int dest, int src) {
- panic("makeRegisterCopy not implemented");
- return 0;
-}
-
template <class CPU>
void zeroRegisters(CPU *cpu);
diff -r bdd926760470 -r 3b0c4b819651 src/arch/power/utility.hh
--- a/src/arch/power/utility.hh Mon Aug 23 09:44:19 2010 -0700
+++ b/src/arch/power/utility.hh Mon Aug 23 16:14:20 2010 -0700
@@ -61,33 +61,6 @@
template <class TC>
void zeroRegisters(TC *tc);
-// Instruction address compression hooks
-static inline Addr
-realPCToFetchPC(const Addr &addr)
-{
- return addr;
-}
-
-static inline Addr
-fetchPCToRealPC(const Addr &addr)
-{
- return addr;
-}
-
-// the size of "fetched" instructions
-static inline size_t
-fetchInstSize()
-{
- return sizeof(MachInst);
-}
-
-static inline MachInst
-makeRegisterCopy(int dest, int src)
-{
- panic("makeRegisterCopy not implemented");
- return 0;
-}
-
inline void
startupCPU(ThreadContext *tc, int cpuId)
{
diff -r bdd926760470 -r 3b0c4b819651 src/arch/sparc/utility.hh
--- a/src/arch/sparc/utility.hh Mon Aug 23 09:44:19 2010 -0700
+++ b/src/arch/sparc/utility.hh Mon Aug 23 16:14:20 2010 -0700
@@ -50,44 +50,6 @@
(tc->readMiscRegNoEffect(MISCREG_HPSTATE) & (1 << 2)));
}
- inline bool isCallerSaveIntegerRegister(unsigned int reg) {
- panic("register classification not implemented");
- return false;
- }
-
- inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
- panic("register classification not implemented");
- return false;
- }
-
- inline bool isCallerSaveFloatRegister(unsigned int reg) {
- panic("register classification not implemented");
- return false;
- }
-
- inline bool isCalleeSaveFloatRegister(unsigned int reg) {
- panic("register classification not implemented");
- return false;
- }
-
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