[m5-dev] changeset in m5: Alpha: Fix Alpha NumMiscArchRegs constant.

[Gabe Black]

changeset addb847910d2 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=addb847910d2
description:
        Alpha: Fix Alpha NumMiscArchRegs constant.

        Also add asserts in O3's Scoreboard class to catch bad indexes.

diffstat:

 src/arch/alpha/registers.hh |   8 ++++----
 src/cpu/o3/scoreboard.cc    |   8 +++++++-
 src/cpu/o3/scoreboard.hh    |  15 +++++++++++++++
 3 files changed, 26 insertions(+), 5 deletions(-)

diffs (109 lines):

diff -r e78b6bba67ca -r addb847910d2 src/arch/alpha/registers.hh
--- a/src/arch/alpha/registers.hh       Fri Oct 01 17:57:56 2010 -0500
+++ b/src/arch/alpha/registers.hh       Mon Oct 04 11:58:06 2010 -0700
@@ -63,7 +63,8 @@
     MISCREG_UNIQ,
     MISCREG_LOCKFLAG,
     MISCREG_LOCKADDR,
-    MISCREG_INTR
+    MISCREG_INTR,
+    NUM_MISCREGS
 };
 
 // semantically meaningful register indices
@@ -84,15 +85,14 @@
 const int NumIntArchRegs = 32;
 const int NumPALShadowRegs = 8;
 const int NumFloatArchRegs = 32;
-// @todo: Figure out what this number really should be.
-const int NumMiscArchRegs = 77;
+const int NumMiscArchRegs = NUM_MISCREGS;
 
 const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs;
 const int NumFloatRegs = NumFloatArchRegs;
 const int NumMiscRegs = NumMiscArchRegs;
 
 const int TotalNumRegs =
-    NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs;
+    NumIntRegs + NumFloatRegs + NumMiscRegs;
 
 const int TotalDataRegs = NumIntRegs + NumFloatRegs;
 
diff -r e78b6bba67ca -r addb847910d2 src/cpu/o3/scoreboard.cc
--- a/src/cpu/o3/scoreboard.cc  Fri Oct 01 17:57:56 2010 -0500
+++ b/src/cpu/o3/scoreboard.cc  Mon Oct 04 11:58:06 2010 -0700
@@ -51,22 +51,25 @@
     numPhysicalRegs = numPhysicalIntRegs  + numPhysicalFloatRegs;
 
     //Resize scoreboard appropriately
-    regScoreBoard.resize(numPhysicalRegs + (numMiscRegs * activeThreads));
+    resize(numPhysicalRegs + (numMiscRegs * activeThreads));
 
     //Initialize values
     for (int i=0; i < numLogicalIntRegs * activeThreads; i++) {
+        assert(indexInBounds(i));
         regScoreBoard[i] = 1;
     }
 
     for (int i= numPhysicalIntRegs;
          i < numPhysicalIntRegs + (numLogicalFloatRegs * activeThreads);
          i++) {
+        assert(indexInBounds(i));
         regScoreBoard[i] = 1;
     }
 
     for (int i = numPhysicalRegs;
          i < numPhysicalRegs + (numMiscRegs * activeThreads);
          i++) {
+        assert(indexInBounds(i));
         regScoreBoard[i] = 1;
     }
 }
@@ -93,6 +96,7 @@
     }
 #endif
 
+    assert(indexInBounds(phys_reg));
     return regScoreBoard[phys_reg];
 }
 
@@ -101,6 +105,7 @@
 {
     DPRINTF(Scoreboard, "Setting reg %i as ready\n", phys_reg);
 
+    assert(indexInBounds(phys_reg));
     regScoreBoard[phys_reg] = 1;
 }
 
@@ -120,5 +125,6 @@
     }
 #endif
 
+    assert(indexInBounds(ready_reg));
     regScoreBoard[ready_reg] = 0;
 }
diff -r e78b6bba67ca -r addb847910d2 src/cpu/o3/scoreboard.hh
--- a/src/cpu/o3/scoreboard.hh  Fri Oct 01 17:57:56 2010 -0500
+++ b/src/cpu/o3/scoreboard.hh  Mon Oct 04 11:58:06 2010 -0700
@@ -111,6 +111,21 @@
 
     /** The logical index of the zero register. */
     int zeroRegIdx;
+
+    int currentSize;
+
+    void
+    resize(int newSize)
+    {
+        currentSize = newSize;
+        regScoreBoard.resize(newSize);
+    }
+
+    bool
+    indexInBounds(int idx)
+    {
+        return idx < currentSize;
+    }
 };
 
 #endif
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