changeset fd65f85fcc0c in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=fd65f85fcc0c
description:
Mem: Change the CLREX flag to CLEAR_LL.
CLREX is the name of an ARM instruction, not a name for this generic
flag.
diffstat:
src/arch/arm/isa/insts/misc.isa | 3 ++-
src/arch/arm/isa/templates/misc.isa | 3 ++-
src/arch/arm/tlb.cc | 4 ++--
src/mem/cache/cache_impl.hh | 4 ++--
src/mem/request.hh | 4 ++--
5 files changed, 10 insertions(+), 8 deletions(-)
diffs (84 lines):
diff -r b5e6461ea242 -r fd65f85fcc0c src/arch/arm/isa/insts/misc.isa
--- a/src/arch/arm/isa/insts/misc.isa Sun Oct 10 20:39:26 2010 -0700
+++ b/src/arch/arm/isa/insts/misc.isa Wed Oct 13 01:57:31 2010 -0700
@@ -671,7 +671,8 @@
exec_output += PredOpExecute.subst(setendIop)
clrexCode = '''
- unsigned memAccessFlags = Request::CLREX|3|Request::LLSC;
+ unsigned memAccessFlags = Request::CLEAR_LL |
+ ArmISA::TLB::AlignWord | Request::LLSC;
fault = xc->read(0, (uint32_t&)Mem, memAccessFlags);
'''
clrexIop = InstObjParams("clrex", "Clrex","PredOp",
diff -r b5e6461ea242 -r fd65f85fcc0c src/arch/arm/isa/templates/misc.isa
--- a/src/arch/arm/isa/templates/misc.isa Sun Oct 10 20:39:26 2010 -0700
+++ b/src/arch/arm/isa/templates/misc.isa Wed Oct 13 01:57:31 2010 -0700
@@ -367,7 +367,8 @@
if (%(predicate_test)s)
{
if (fault == NoFault) {
- unsigned memAccessFlags = Request::CLREX|3|Request::LLSC;
+ unsigned memAccessFlags = Request::CLEAR_LL |
+ ArmISA::TLB::AlignWord | Request::LLSC;
fault = xc->read(0, (uint32_t&)Mem, memAccessFlags);
}
} else {
diff -r b5e6461ea242 -r fd65f85fcc0c src/arch/arm/tlb.cc
--- a/src/arch/arm/tlb.cc Sun Oct 10 20:39:26 2010 -0700
+++ b/src/arch/arm/tlb.cc Wed Oct 13 01:57:31 2010 -0700
@@ -376,10 +376,10 @@
// If this is a clrex instruction, provide a PA of 0 with no fault
// This will force the monitor to set the tracked address to 0
// a bit of a hack but this effectively clrears this processors monitor
- if (flags & Request::CLREX){
+ if (flags & Request::CLEAR_LL){
req->setPaddr(0);
req->setFlags(Request::UNCACHEABLE);
- req->setFlags(Request::CLREX);
+ req->setFlags(Request::CLEAR_LL);
return NoFault;
}
if ((req->isInstFetch() && (!sctlr.i)) ||
diff -r b5e6461ea242 -r fd65f85fcc0c src/mem/cache/cache_impl.hh
--- a/src/mem/cache/cache_impl.hh Sun Oct 10 20:39:26 2010 -0700
+++ b/src/mem/cache/cache_impl.hh Wed Oct 13 01:57:31 2010 -0700
@@ -306,7 +306,7 @@
int &lat, PacketList &writebacks)
{
if (pkt->req->isUncacheable()) {
- if (pkt->req->isClrex()) {
+ if (pkt->req->isClearLL()) {
tags->clearLocks();
} else {
blk = tags->findBlock(pkt->getAddr());
@@ -449,7 +449,7 @@
}
if (pkt->req->isUncacheable()) {
- if (pkt->req->isClrex()) {
+ if (pkt->req->isClearLL()) {
tags->clearLocks();
} else {
BlkType *blk = tags->findBlock(pkt->getAddr());
diff -r b5e6461ea242 -r fd65f85fcc0c src/mem/request.hh
--- a/src/mem/request.hh Sun Oct 10 20:39:26 2010 -0700
+++ b/src/mem/request.hh Wed Oct 13 01:57:31 2010 -0700
@@ -72,7 +72,7 @@
/** This request is to a memory mapped register. */
static const FlagsType MMAPED_IPR = 0x00002000;
/** This request is a clear exclusive. */
- static const FlagsType CLREX = 0x00004000;
+ static const FlagsType CLEAR_LL = 0x00004000;
/** The request should ignore unaligned access faults */
static const FlagsType NO_ALIGN_FAULT = 0x00020000;
@@ -458,7 +458,7 @@
bool isSwap() const { return _flags.isSet(MEM_SWAP|MEM_SWAP_COND); }
bool isCondSwap() const { return _flags.isSet(MEM_SWAP_COND); }
bool isMmapedIpr() const { return _flags.isSet(MMAPED_IPR); }
- bool isClrex() const { return _flags.isSet(CLREX); }
+ bool isClearLL() const { return _flags.isSet(CLEAR_LL); }
bool
isMisaligned() const
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