On Oct 19, 2010, at 11:14 PM, Ali Saidi wrote: > > >> On 2010-10-09 13:38:40, Gabe Black wrote: >>> src/cpu/simple/timing.cc, line 765 >>> <http://reviews.m5sim.org/r/256/diff/1/?file=3666#file3666line765> >>> >>> Prefetch faults should ideally be surpressed at their source, not here. >>> At the source we already implicitly know the instruction shouldn't fault. >>> Here, we have to rediscover that all the time. >> >> Ali Saidi wrote: >> I don't agree. If you suppress this at the source the CPU model doesn't >> know if it should actually try and issue the instruction, so that would have >> to be checked some how. Additionally, in most cases there is one or two >> place in the TLB that a correct translation is returned and as many places >> where a fault is returned. Checking there would complication all of the code >> paths. >> >> Steve Reinhardt wrote: >> I don't follow your argument... shouldn't the prefetch get issued >> unconditionally? If it doesn't have a valid translation then you don't want >> to send it to the cache, but the instruction itself still gets executed. >> >> As far as implementing this, seems like there could be just one or two >> places after the TLB translation is returned where we override the fault if >> it's a prefetch, rather than pushing the override into the TLB itself. >> > > I think the prefetch should be sent the the TLB unconditionally, and then if > the prefetch faults the CPU should toss the instruction rather than the TLB > returning no fault and the CPU i guess checking if the PA is set? > > I agree that we should override the fault in the CPU. Are we violently > agreeing?
bump... bump... Ali _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
