changeset ba11187e2582 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=ba11187e2582
description:
ARM: Make all ARM uops delayed commit.
diffstat:
src/arch/arm/insts/macromem.hh | 6 ------
src/arch/arm/isa/templates/mem.isa | 19 +++++++++++++++++++
src/cpu/static_inst.hh | 2 ++
3 files changed, 21 insertions(+), 6 deletions(-)
diffs (154 lines):
diff -r ee4ac00d0774 -r ba11187e2582 src/arch/arm/insts/macromem.hh
--- a/src/arch/arm/insts/macromem.hh Mon Nov 08 13:58:22 2010 -0600
+++ b/src/arch/arm/insts/macromem.hh Mon Nov 08 13:58:22 2010 -0600
@@ -73,12 +73,6 @@
public:
void
- setDelayedCommit()
- {
- flags[IsDelayedCommit] = true;
- }
-
- void
advancePC(PCState &pcState) const
{
if (flags[IsLastMicroop]) {
diff -r ee4ac00d0774 -r ba11187e2582 src/arch/arm/isa/templates/mem.isa
--- a/src/arch/arm/isa/templates/mem.isa Mon Nov 08 13:58:22 2010 -0600
+++ b/src/arch/arm/isa/templates/mem.isa Mon Nov 08 13:58:22 2010 -0600
@@ -917,6 +917,7 @@
assert(numMicroops >= 2);
uops = new StaticInstPtr[numMicroops];
uops[0] = new %(acc_name)s(machInst, _base, _mode, _wb);
+ uops[0]->setDelayedCommit();
uops[1] = new %(wb_decl)s;
uops[1]->setLastMicroop();
#endif
@@ -934,6 +935,7 @@
assert(numMicroops >= 2);
uops = new StaticInstPtr[numMicroops];
uops[0] = new %(acc_name)s(machInst, _regMode, _mode, _wb);
+ uops[0]->setDelayedCommit();
uops[1] = new %(wb_decl)s;
uops[1]->setLastMicroop();
#endif
@@ -963,6 +965,7 @@
assert(numMicroops >= 2);
uops = new StaticInstPtr[numMicroops];
uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, _imm);
+ uops[0]->setDelayedCommit();
uops[1] = new %(wb_decl)s;
uops[1]->setLastMicroop();
#endif
@@ -984,6 +987,7 @@
uops = new StaticInstPtr[numMicroops];
uops[0] = new %(acc_name)s(machInst, _result, _dest, _dest2,
_base, _add, _imm);
+ uops[0]->setDelayedCommit();
uops[1] = new %(wb_decl)s;
uops[1]->setLastMicroop();
#endif
@@ -1001,6 +1005,7 @@
assert(numMicroops >= 2);
uops = new StaticInstPtr[numMicroops];
uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm);
+ uops[0]->setDelayedCommit();
uops[1] = new %(wb_decl)s;
uops[1]->setLastMicroop();
#endif
@@ -1021,6 +1026,7 @@
uops = new StaticInstPtr[numMicroops];
uops[0] = new %(acc_name)s(machInst, _result, _dest,
_base, _add, _imm);
+ uops[0]->setDelayedCommit();
uops[1] = new %(wb_decl)s;
uops[1]->setLastMicroop();
#endif
@@ -1043,6 +1049,7 @@
uops = new StaticInstPtr[numMicroops];
uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add,
_shiftAmt, _shiftType, _index);
+ uops[0]->setDelayedCommit();
uops[1] = new %(wb_decl)s;
uops[1]->setLastMicroop();
#endif
@@ -1064,6 +1071,7 @@
uops = new StaticInstPtr[numMicroops];
uops[0] = new %(acc_name)s(machInst, _dest, _base, _add,
_shiftAmt, _shiftType, _index);
+ uops[0]->setDelayedCommit();
uops[1] = new %(wb_decl)s;
uops[1]->setLastMicroop();
#endif
@@ -1087,14 +1095,17 @@
if ((_dest == _index) || (_dest2 == _index)) {
IntRegIndex wbIndexReg = INTREG_UREG0;
uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index);
+ uops[0]->setDelayedCommit();
uops[1] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add,
_shiftAmt, _shiftType, _index);
+ uops[1]->setDelayedCommit();
uops[2] = new %(wb_decl)s;
uops[2]->setLastMicroop();
} else {
IntRegIndex wbIndexReg = index;
uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add,
_shiftAmt, _shiftType, _index);
+ uops[0]->setDelayedCommit();
uops[1] = new %(wb_decl)s;
uops[1]->setLastMicroop();
}
@@ -1119,20 +1130,25 @@
IntRegIndex wbIndexReg = index;
uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add,
_shiftAmt, _shiftType, _index);
+ uops[0]->setDelayedCommit();
uops[1] = new %(wb_decl)s;
+ uops[1]->setDelayedCommit();
uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0);
uops[2]->setLastMicroop();
} else if(_dest == _index) {
IntRegIndex wbIndexReg = INTREG_UREG0;
uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index);
+ uops[0]->setDelayedCommit();
uops[1] = new %(acc_name)s(machInst, _dest, _base, _add,
_shiftAmt, _shiftType, _index);
+ uops[1]->setDelayedCommit();
uops[2] = new %(wb_decl)s;
uops[2]->setLastMicroop();
} else {
IntRegIndex wbIndexReg = index;
uops[0] = new %(acc_name)s(machInst, _dest, _base, _add,
_shiftAmt, _shiftType, _index);
+ uops[0]->setDelayedCommit();
uops[1] = new %(wb_decl)s;
uops[1]->setLastMicroop();
@@ -1154,11 +1170,14 @@
if (_dest == INTREG_PC) {
uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add,
_imm);
+ uops[0]->setDelayedCommit();
uops[1] = new %(wb_decl)s;
+ uops[1]->setDelayedCommit();
uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0);
uops[2]->setLastMicroop();
} else {
uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm);
+ uops[0]->setDelayedCommit();
uops[1] = new %(wb_decl)s;
uops[1]->setLastMicroop();
}
diff -r ee4ac00d0774 -r ba11187e2582 src/cpu/static_inst.hh
--- a/src/cpu/static_inst.hh Mon Nov 08 13:58:22 2010 -0600
+++ b/src/cpu/static_inst.hh Mon Nov 08 13:58:22 2010 -0600
@@ -263,6 +263,8 @@
//@}
void setLastMicroop() { flags[IsLastMicroop] = true; }
+ void setDelayedCommit() { flags[IsDelayedCommit] = true; }
+
/// Operation class. Used to select appropriate function unit in issue.
OpClass opClass() const { return _opClass; }
};
_______________________________________________
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
