changeset 0d9de7394e38 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=0d9de7394e38 description: ARM/Alpha/Cpu: Stats change for prefetchs to be more like normal loads.
diffstat: tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini | 4 +- tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout | 14 +- tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt | 642 +- tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini | 2 +- tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr | 3 + tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout | 11 +- tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt | 10 +- tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini | 4 +- tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout | 12 +- tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt | 10 +- tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini | 12 +- tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout | 17 +- tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt | 1782 +++++----- tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini | 12 +- tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout | 17 +- tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt | 979 ++-- tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini | 4 +- tests/long/30.eon/ref/alpha/tru64/o3-timing/simout | 14 +- tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt | 590 +- tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini | 2 +- tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr | 3 + tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout | 11 +- tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt | 10 +- tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini | 4 +- tests/long/30.eon/ref/alpha/tru64/simple-timing/simout | 12 +- tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt | 10 +- tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini | 4 +- tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout | 14 +- tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt | 616 +- tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini | 2 +- tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr | 3 + tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout | 11 +- tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt | 10 +- tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini | 4 +- tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout | 12 +- tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt | 10 +- tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini | 4 +- tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simerr | 4 - tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout | 12 +- tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt | 24 +- tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini | 4 +- tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout | 14 +- tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt | 636 +- tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini | 2 +- tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr | 3 + tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout | 11 +- tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt | 10 +- tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini | 4 +- tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout | 12 +- tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt | 10 +- tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini | 4 +- tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout | 14 +- tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt | 648 +- tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini | 2 +- tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simerr | 3 + tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout | 11 +- tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt | 10 +- tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini | 4 +- tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout | 12 +- tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt | 10 +- tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini | 4 +- tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simerr | 4 - tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout | 13 +- tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt | 30 +- tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini | 4 +- tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout | 15 +- tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt | 624 +- tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini | 2 +- tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simerr | 3 + tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout | 12 +- tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt | 10 +- tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini | 4 +- tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout | 12 +- tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt | 10 +- tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini | 2 +- tests/quick/00.hello/ref/alpha/linux/o3-timing/simout | 14 +- tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt | 38 +- tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini | 2 +- tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout | 10 +- tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt | 6 +- tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini | 12 +- tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout | 15 +- tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt | 12 +- tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini | 12 +- tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout | 15 +- tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt | 10 +- tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini | 12 +- tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout | 15 +- tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt | 12 +- tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini | 12 +- tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout | 15 +- tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt | 10 +- tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr | 14 +- tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout | 15 +- tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt | 48 - tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr | 14 +- tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout | 17 +- tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt | 231 - tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr | 20 +- tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout | 23 +- tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt | 710 --- tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr | 20 +- tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout | 23 +- tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt | 810 ---- tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini | 44 +- tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal | 2 +- tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout | 16 +- tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt | 18 +- tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal | 2 +- 109 files changed, 3795 insertions(+), 5548 deletions(-) diffs (truncated from 12481 to 300 lines): diff -r 00ea9430643b -r 0d9de7394e38 tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini Mon Nov 08 13:58:22 2010 -0600 +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini Mon Nov 08 13:58:24 2010 -0600 @@ -353,12 +353,12 @@ [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing +cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing egid=100 env= errout=cerr euid=100 -executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/gzip +executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip gid=100 input=cin max_stack_size=67108864 diff -r 00ea9430643b -r 0d9de7394e38 tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout Mon Nov 08 13:58:22 2010 -0600 +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout Mon Nov 08 13:58:24 2010 -0600 @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,11 +7,11 @@ All Rights Reserved -M5 compiled Sep 20 2010 15:04:49 -M5 revision 0c4a7d867247 7686 default qtip print-identical tip -M5 started Sep 20 2010 15:56:01 -M5 executing on phenom -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing +M5 compiled Nov 2 2010 21:30:55 +M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip +M5 started Nov 2 2010 22:21:55 +M5 executing on aus-bc2-b15 +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -44,4 +46,4 @@ Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 165376986500 because target called exit() +Exiting @ tick 162779779500 because target called exit() diff -r 00ea9430643b -r 0d9de7394e38 tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt Mon Nov 08 13:58:22 2010 -0600 +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt Mon Nov 08 13:58:24 2010 -0600 @@ -1,339 +1,339 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 264030 # Simulator instruction rate (inst/s) -host_mem_usage 193748 # Number of bytes of host memory used -host_seconds 2142.00 # Real time elapsed on the host -host_tick_rate 77206740 # Simulator tick rate (ticks/s) +host_inst_rate 299092 # Simulator instruction rate (inst/s) +host_mem_usage 240504 # Number of bytes of host memory used +host_seconds 1890.90 # Real time elapsed on the host +host_tick_rate 86086026 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 565552443 # Number of instructions simulated -sim_seconds 0.165377 # Number of seconds simulated -sim_ticks 165376986500 # Number of ticks simulated +sim_seconds 0.162780 # Number of seconds simulated +sim_ticks 162779779500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 63929788 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 71429024 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 197 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 4120838 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 70454375 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 76396550 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 1676108 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.BTBHits 63926991 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 71320793 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 193 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 4120736 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 70355271 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 76295210 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 1675650 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 62547159 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 20033371 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 19927815 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 320816297 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.876017 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 2.306184 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 315794082 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.905853 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 2.338192 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 102501444 31.95% 31.95% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 105613320 32.92% 64.87% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 36739083 11.45% 76.32% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 11050019 3.44% 79.77% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 10174748 3.17% 82.94% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 21768321 6.79% 89.72% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 10744082 3.35% 93.07% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 2191909 0.68% 93.76% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 20033371 6.24% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 102454006 32.44% 32.44% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 100543040 31.84% 64.28% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 36844526 11.67% 75.95% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 9307171 2.95% 78.90% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 10247874 3.25% 82.14% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 21736977 6.88% 89.02% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 12524254 3.97% 92.99% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 2208419 0.70% 93.69% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 19927815 6.31% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 320816297 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 315794082 # Number of insts commited each cycle system.cpu.commit.COM:count 601856963 # Number of instructions committed -system.cpu.commit.COM:loads 115049510 # Number of loads committed +system.cpu.commit.COM:loads 114514042 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 154862033 # Number of memory references committed +system.cpu.commit.COM:refs 153965363 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 4120001 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 4119890 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 61749735 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 60520337 # The number of squashed insts skipped by commit system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.584833 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.584833 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 4 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits 4 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 115012927 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 14990.355830 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7392.342173 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 114228619 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 11757056000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.006819 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 784308 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 566126 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1612876000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001897 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 218182 # number of ReadReq MSHR misses +system.cpu.cpi 0.575649 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.575649 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits 3 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_accesses 112312480 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 15160.742892 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7367.811163 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 111525313 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 11934036500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.007009 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 787167 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 569138 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1606396500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001941 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 218029 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 14906.098057 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11053.696113 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 38301940 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 17132785891 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.029134 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1149381 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 892463 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2839893498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 14279.189894 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11300.460826 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 38165820 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 18355912888 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.032584 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1285501 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1028584 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 2903280494 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.006512 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 256918 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6663.699115 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_mshr_misses 256917 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 7297.150943 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 20363.636364 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 321.049385 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 113 # number of cycles access was blocked +system.cpu.dcache.avg_refs 315.175064 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 106 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 752998 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 773498 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 224000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 154464248 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 14940.273173 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 9372.278463 # average overall mshr miss latency -system.cpu.dcache.demand_hits 152530559 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 28889841891 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.012519 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1933689 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 1458589 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 4452769498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.003076 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 475100 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 151763801 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 14613.989982 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 9495.136277 # average overall mshr miss latency +system.cpu.dcache.demand_hits 149691133 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 30289949388 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.013657 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2072668 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 1597722 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 4509676994 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.003130 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 474946 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999558 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4094.188781 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 154464248 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 14940.273173 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 9372.278463 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.999550 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4094.156298 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 151763801 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 14613.989982 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 9495.136277 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 152530559 # number of overall hits -system.cpu.dcache.overall_miss_latency 28889841891 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.012519 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1933689 # number of overall misses -system.cpu.dcache.overall_mshr_hits 1458589 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 4452769498 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.003076 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 475100 # number of overall MSHR misses +system.cpu.dcache.overall_hits 149691133 # number of overall hits +system.cpu.dcache.overall_miss_latency 30289949388 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.013657 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2072668 # number of overall misses +system.cpu.dcache.overall_mshr_hits 1597722 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 4509676994 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.003130 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 474946 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 471004 # number of replacements -system.cpu.dcache.sampled_refs 475100 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 470850 # number of replacements +system.cpu.dcache.sampled_refs 474946 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.188781 # Cycle average of tags in use -system.cpu.dcache.total_refs 152530563 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 126404000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 423151 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 48113828 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 871 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 4177876 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 689990711 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 144277716 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 122985866 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 9844039 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 3043 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 5438887 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 163094811 # DTB accesses +system.cpu.dcache.tagsinuse 4094.156298 # Cycle average of tags in use +system.cpu.dcache.total_refs 149691136 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 126698000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 423042 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 45000094 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 877 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 4176202 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 688674202 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 142513181 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 122905016 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 9698747 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 3338 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 5375791 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 163053496 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 163045966 # DTB hits -system.cpu.dtb.data_misses 48845 # DTB misses +system.cpu.dtb.data_hits 163001268 # DTB hits +system.cpu.dtb.data_misses 52228 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 122278185 # DTB read accesses +system.cpu.dtb.read_accesses 122206073 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 122255138 # DTB read hits -system.cpu.dtb.read_misses 23047 # DTB read misses -system.cpu.dtb.write_accesses 40816626 # DTB write accesses +system.cpu.dtb.read_hits 122181392 # DTB read hits +system.cpu.dtb.read_misses 24681 # DTB read misses _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev