changeset e1eace3a118a in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=e1eace3a118a description: ARM: Keep the warnings to a minimum.
These warnings still need to be addresses, but pages of them is counterproductive. diffstat: src/arch/arm/isa.cc | 14 +++++++------- src/dev/arm/RealView.py | 2 +- 2 files changed, 8 insertions(+), 8 deletions(-) diffs (71 lines): diff -r 982b4c6c1470 -r e1eace3a118a src/arch/arm/isa.cc --- a/src/arch/arm/isa.cc Mon Nov 08 13:58:24 2010 -0600 +++ b/src/arch/arm/isa.cc Mon Nov 08 13:58:24 2010 -0600 @@ -180,10 +180,10 @@ } switch (misc_reg) { case MISCREG_CLIDR: - warn("The clidr register always reports 0 caches.\n"); + warn_once("The clidr register always reports 0 caches.\n"); break; case MISCREG_CCSIDR: - warn("The ccsidr register isn't implemented and " + warn_once("The ccsidr register isn't implemented and " "always reads as 0.\n"); break; case MISCREG_ID_PFR0: @@ -268,7 +268,7 @@ } break; case MISCREG_CSSELR: - warn("The csselr register isn't implemented.\n"); + warn_once("The csselr register isn't implemented.\n"); break; case MISCREG_FPSCR: { @@ -319,7 +319,7 @@ return; case MISCREG_TLBIALLIS: case MISCREG_TLBIALL: - warn("Need to flush all TLBs in MP\n"); + warn_once("Need to flush all TLBs in MP\n"); tc->getITBPtr()->flushAll(); tc->getDTBPtr()->flushAll(); return; @@ -331,7 +331,7 @@ return; case MISCREG_TLBIMVAIS: case MISCREG_TLBIMVA: - warn("Need to flush all TLBs in MP\n"); + warn_once("Need to flush all TLBs in MP\n"); tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), bits(newVal, 7,0)); tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), @@ -339,13 +339,13 @@ return; case MISCREG_TLBIASIDIS: case MISCREG_TLBIASID: - warn("Need to flush all TLBs in MP\n"); + warn_once("Need to flush all TLBs in MP\n"); tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); return; case MISCREG_TLBIMVAAIS: case MISCREG_TLBIMVAA: - warn("Need to flush all TLBs in MP\n"); + warn_once("Need to flush all TLBs in MP\n"); tc->getITBPtr()->flushMva(mbits(newVal, 31,12)); tc->getDTBPtr()->flushMva(mbits(newVal, 31,12)); return; diff -r 982b4c6c1470 -r e1eace3a118a src/dev/arm/RealView.py --- a/src/dev/arm/RealView.py Mon Nov 08 13:58:24 2010 -0600 +++ b/src/dev/arm/RealView.py Mon Nov 08 13:58:24 2010 -0600 @@ -100,7 +100,7 @@ timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) - l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1") + l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff) flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x4000000) dmac_fake = AmbaFake(pio_addr=0x10030000) uart1_fake = AmbaFake(pio_addr=0x1000a000) _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev