> On 2010-11-09 11:37:23, Gabe Black wrote: > > src/cpu/simple_thread.cc, line 159 > > <http://reviews.m5sim.org/r/290/diff/1/?file=5049#file5049line159> > > > > What happens to the old TLB? What if you wanted to switch to a new one? > > I'm assuming this is so state cached in the TLB gets transfered, but I > > don't think this is the right way to do it. Maybe in the copyRegs function > > you can transfer state between TLBs? Maybe it already is because you're > > updating miscregs, and that should update the TLB. Maybe you need to set > > more miscregs with effects.
In this case you keep the old TLB. I this this is really desired behavior, because you want that structure to be warmed up on the switch and if you switch to a new one it's empty. It's also so whatever the TLB is connected to it stays connected. In the case of ISAs that require table walkers the code would need to figure that out and move their ports too. - Ali ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/290/#review443 ----------------------------------------------------------- On 2010-11-08 15:27:44, Ali Saidi wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/290/ > ----------------------------------------------------------- > > (Updated 2010-11-08 15:27:44) > > > Review request for Default. > > > Summary > ------- > > ARM: Add support for switching CPUs > > > Diffs > ----- > > src/arch/arm/table_walker.hh f61e079ad05e > src/arch/arm/table_walker.cc f61e079ad05e > src/arch/arm/utility.hh f61e079ad05e > src/arch/arm/utility.cc f61e079ad05e > src/cpu/simple_thread.cc f61e079ad05e > > Diff: http://reviews.m5sim.org/r/290/diff > > > Testing > ------- > > > Thanks, > > Ali > > _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
