Sorry about that. Do you need to fix it, or me? It may be simpler if you do.
That also brings up the question of testing with ARM. Internal to ARM
testing is fairly sophisticated and gets at most of what's implemented
instruction wise. External to ARM testing is much less so, so it's
hard to know whether something broke. I don't have any suggestions
there, but it would be nice to bring those into alignment somehow.
Maybe an FS regression would cover a lot of the gaps? I'm pretty sure
that's in the works, right?
Gabe
Quoting Ali Saidi <[email protected]>:
Turns out this isn't entirely correct.
SRS is writing back in initiateAcc() and your change fe91d5e2c374
unfortunately breaks those cases. It really shouldn't be doing this,
it either needs to do it in completeAcc or needs to be a macro-op,
but it broke some stuff.
Ali
On Tue, 19 Oct 2010 15:24:56 -0700, Gabe Black <[email protected]> wrote:
I've been surveying all the ISAs to see how they're using initiateAcc
and completeAcc, and it looks like there are two cases where completeAcc
needs to be (and apparently is) called on stores or store like
instructions. The first are the StoreConditional instructions which have
to (at least in some cases) write whether the store succeeded somewhere.
The second are the swap instructions which have to write the old value
of memory to a register. I don't expect this to be a revelation for
anyone and it's not the source of any problems, but I wanted to verify
what I'm saying here is correct and see if anyone can think of any other
places where completeAcc needs to be called.
I've verified, as best I can by inspection, that initiateAcc isn't doing
any writing back of registers. That's good, because that wouldn't work
anyway. Some templates in ARM make it look like it might, but that's
just from copy/paste, I think, and tracing back to where the templates
get filled in and with what, there shouldn't be any registers to write.
Gabe
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