changeset 5c374c1e0075 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=5c374c1e0075
description:
ARM: Update regressions for CLCD and KMI additions
diffstat:
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
| 73 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
| 10 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
| 330 +++---
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status
| 2 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal
| 0
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
| 73 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
| 10 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
| 512 +++++-----
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal
| 0
9 files changed, 514 insertions(+), 496 deletions(-)
diffs (truncated from 1627 to 300 lines):
diff -r 8ae6f4055594 -r 5c374c1e0075
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
Mon Nov 15 14:04:03 2010 -0600
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
Mon Nov 15 14:04:03 2010 -0600
@@ -178,7 +178,7 @@
header_cycles=1
use_default_range=false
width=64
-port=system.bridge.side_a system.realview.uart.pio
system.realview.realview_io.pio system.realview.timer0.pio
system.realview.timer1.pio system.realview.dmac_fake.pio
system.realview.uart1_fake.pio system.realview.uart2_fake.pio
system.realview.uart3_fake.pio system.realview.smc_fake.pio
system.realview.clcd_fake.pio system.realview.sp810_fake.pio
system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio
system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio
system.realview.ssp_fake.pio system.realview.sci_fake.pio
system.realview.aaci_fake.pio system.realview.mmc_fake.pio
system.realview.kmi0_fake.pio system.realview.kmi1_fake.pio
system.realview.rtc_fake.pio system.realview.flash_fake.pio
system.iocache.cpu_side
+port=system.bridge.side_a system.realview.uart.pio
system.realview.realview_io.pio system.realview.timer0.pio
system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio
system.realview.kmi1.pio system.realview.dmac_fake.pio
system.realview.uart1_fake.pio system.realview.uart2_fake.pio
system.realview.uart3_fake.pio system.realview.smc_fake.pio
system.realview.sp810_fake.pio system.realview.watchdog_fake.pio
system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio
system.realview.gpio2_fake.pio system.realview.ssp_fake.pio
system.realview.sci_fake.pio system.realview.aaci_fake.pio
system.realview.mmc_fake.pio system.realview.rtc_fake.pio
system.realview.flash_fake.pio system.iocache.cpu_side system.realview.clcd.dma
[system.iocache]
type=BaseCache
@@ -282,7 +282,7 @@
[system.realview]
type=RealView
-children=aaci_fake clcd_fake dmac_fake flash_fake gic gpio0_fake gpio1_fake
gpio2_fake kmi0_fake kmi1_fake l2x0_fake mmc_fake realview_io rtc_fake sci_fake
smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake
uart3_fake watchdog_fake
+children=aaci_fake clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake
gpio2_fake kmi0 kmi1 l2x0_fake mmc_fake realview_io rtc_fake sci_fake smc_fake
sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake
watchdog_fake
intrctrl=system.intrctrl
system=system
@@ -294,17 +294,22 @@
pio_latency=1000
platform=system.realview
system=system
-pio=system.iobus.port[18]
+pio=system.iobus.port[20]
-[system.realview.clcd_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
+[system.realview.clcd]
+type=Pl111
+amba_id=1315089
+clock=41667
+gic=system.realview.gic
+int_num=55
+max_backoff_delay=10000000
+min_backoff_delay=4000
pio_addr=268566528
-pio_latency=1000
+pio_latency=10000
platform=system.realview
system=system
-pio=system.iobus.port[10]
+dma=system.iobus.port[25]
+pio=system.iobus.port[5]
[system.realview.dmac_fake]
type=AmbaFake
@@ -314,7 +319,7 @@
pio_latency=1000
platform=system.realview
system=system
-pio=system.iobus.port[5]
+pio=system.iobus.port[8]
[system.realview.flash_fake]
type=IsaFake
@@ -351,7 +356,7 @@
pio_latency=1000
platform=system.realview
system=system
-pio=system.iobus.port[13]
+pio=system.iobus.port[15]
[system.realview.gpio1_fake]
type=AmbaFake
@@ -361,7 +366,7 @@
pio_latency=1000
platform=system.realview
system=system
-pio=system.iobus.port[14]
+pio=system.iobus.port[16]
[system.realview.gpio2_fake]
type=AmbaFake
@@ -371,27 +376,31 @@
pio_latency=1000
platform=system.realview
system=system
-pio=system.iobus.port[15]
+pio=system.iobus.port[17]
-[system.realview.kmi0_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
+[system.realview.kmi0]
+type=Pl050
+amba_id=1314896
+gic=system.realview.gic
+int_delay=100000
+int_num=52
pio_addr=268460032
pio_latency=1000
platform=system.realview
system=system
-pio=system.iobus.port[20]
+pio=system.iobus.port[6]
-[system.realview.kmi1_fake]
-type=AmbaFake
-amba_id=0
-ignore_access=false
+[system.realview.kmi1]
+type=Pl050
+amba_id=1314896
+gic=system.realview.gic
+int_delay=100000
+int_num=53
pio_addr=268464128
pio_latency=1000
platform=system.realview
system=system
-pio=system.iobus.port[21]
+pio=system.iobus.port[7]
[system.realview.l2x0_fake]
type=IsaFake
@@ -417,7 +426,7 @@
pio_latency=1000
platform=system.realview
system=system
-pio=system.iobus.port[19]
+pio=system.iobus.port[21]
[system.realview.realview_io]
type=RealViewCtrl
@@ -446,7 +455,7 @@
pio_latency=1000
platform=system.realview
system=system
-pio=system.iobus.port[17]
+pio=system.iobus.port[19]
[system.realview.smc_fake]
type=AmbaFake
@@ -456,7 +465,7 @@
pio_latency=1000
platform=system.realview
system=system
-pio=system.iobus.port[9]
+pio=system.iobus.port[12]
[system.realview.sp810_fake]
type=AmbaFake
@@ -466,7 +475,7 @@
pio_latency=1000
platform=system.realview
system=system
-pio=system.iobus.port[11]
+pio=system.iobus.port[13]
[system.realview.ssp_fake]
type=AmbaFake
@@ -476,7 +485,7 @@
pio_latency=1000
platform=system.realview
system=system
-pio=system.iobus.port[16]
+pio=system.iobus.port[18]
[system.realview.timer0]
type=Sp804
@@ -527,7 +536,7 @@
pio_latency=1000
platform=system.realview
system=system
-pio=system.iobus.port[6]
+pio=system.iobus.port[9]
[system.realview.uart2_fake]
type=AmbaFake
@@ -537,7 +546,7 @@
pio_latency=1000
platform=system.realview
system=system
-pio=system.iobus.port[7]
+pio=system.iobus.port[10]
[system.realview.uart3_fake]
type=AmbaFake
@@ -547,7 +556,7 @@
pio_latency=1000
platform=system.realview
system=system
-pio=system.iobus.port[8]
+pio=system.iobus.port[11]
[system.realview.watchdog_fake]
type=AmbaFake
@@ -557,7 +566,7 @@
pio_latency=1000
platform=system.realview
system=system
-pio=system.iobus.port[12]
+pio=system.iobus.port[14]
[system.terminal]
type=Terminal
diff -r 8ae6f4055594 -r 5c374c1e0075
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
Mon Nov 15 14:04:03 2010 -0600
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
Mon Nov 15 14:04:03 2010 -0600
@@ -5,12 +5,12 @@
All Rights Reserved
-M5 compiled Oct 1 2010 22:55:27
-M5 revision 8dd1bd50f739 7724 default qtip tip
ext/vfp_serial_nonspec_flags.patch
-M5 started Oct 1 2010 23:07:06
-M5 executing on aus-bc3-b7
+M5 compiled Oct 15 2010 11:17:32
+M5 revision e459beb39dd0 7713 default ext/amba_kmi_pl050.patch qtip tip
+M5 started Oct 15 2010 11:17:48
+M5 executing on aus-bc3-b4
command line: build/ARM_FS/m5.opt -d
build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic -re
tests/run.py
build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 25749159000 because m5_exit instruction encountered
+Exiting @ tick 25821310500 because m5_exit instruction encountered
diff -r 8ae6f4055594 -r 5c374c1e0075
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
Mon Nov 15 14:04:03 2010 -0600
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
Mon Nov 15 14:04:03 2010 -0600
@@ -1,63 +1,63 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1902681 #
Simulator instruction rate (inst/s)
-host_mem_usage 378772 #
Number of bytes of host memory used
-host_seconds 26.70 #
Real time elapsed on the host
-host_tick_rate 964308738 #
Simulator tick rate (ticks/s)
+host_inst_rate 1831927 #
Simulator instruction rate (inst/s)
+host_mem_usage 384484 #
Number of bytes of host memory used
+host_seconds 27.81 #
Real time elapsed on the host
+host_tick_rate 928414614 #
Simulator tick rate (ticks/s)
sim_freq 1000000000000 #
Frequency of simulated ticks
-sim_insts 50805202 #
Number of instructions simulated
-sim_seconds 0.025749 #
Number of seconds simulated
-sim_ticks 25749159000 #
Number of ticks simulated
-system.cpu.dcache.LoadLockedReq_accesses::0 96510
# number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 96510
# number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits::0 91456 #
number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 91456
# number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_rate::0 0.052368
# miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses::0 5054 #
number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 5054
# number of LoadLockedReq misses
-system.cpu.dcache.ReadReq_accesses::0 7686910 #
number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 7686910 #
number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_hits::0 7455461 #
number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 7455461 #
number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_rate::0 0.030109 #
miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::0 231449 #
number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 231449 #
number of ReadReq misses
-system.cpu.dcache.StoreCondReq_accesses::0 96509
# number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 96509
# number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits::0 96509 #
number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 96509
# number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses::0 6583516 #
number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 6583516
# number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_hits::0 6409119 #
number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 6409119 #
number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_rate::0 0.026490 #
miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::0 174397 #
number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 174397 #
number of WriteReq misses
+sim_insts 50949504 #
Number of instructions simulated
+sim_seconds 0.025821 #
Number of seconds simulated
+sim_ticks 25821310500 #
Number of ticks simulated
+system.cpu.dcache.LoadLockedReq_accesses::0 96794
# number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 96794
# number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_hits::0 91895 #
number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 91895
# number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_miss_rate::0 0.050613
# miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_misses::0 4899 #
number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 4899
# number of LoadLockedReq misses
+system.cpu.dcache.ReadReq_accesses::0 7714516 #
number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 7714516 #
number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_hits::0 7482193 #
number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 7482193 #
number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_rate::0 0.030115 #
miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses::0 232323 #
number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 232323 #
number of ReadReq misses
+system.cpu.dcache.StoreCondReq_accesses::0 96793
# number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 96793
# number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_hits::0 96793 #
number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 96793
# number of StoreCondReq hits
+system.cpu.dcache.WriteReq_accesses::0 6604860 #
number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 6604860
# number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_hits::0 6433311 #
number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 6433311 #
number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_rate::0 0.025973 #
miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses::0 171549 #
number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 171549 #
number of WriteReq misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
# average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value
# average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 34.349377 #
Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 34.663994 #
Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 #
number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 #
number of cycles access was blocked
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev
