changeset d7360f5052b2 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=d7360f5052b2
description:
ARM: Return an FailUnimp instruction when an unimplemented CP15
register is accessed.
Just panicing in readMiscReg() doesn't work because a speculative access
in the o3 model can end the simulation.
diffstat:
src/arch/arm/isa.cc | 5 ++---
src/arch/arm/isa/formats/misc.isa | 4 ++++
2 files changed, 6 insertions(+), 3 deletions(-)
diffs (31 lines):
diff -r 846fb3ffe0dc -r d7360f5052b2 src/arch/arm/isa.cc
--- a/src/arch/arm/isa.cc Mon Nov 15 14:04:04 2010 -0600
+++ b/src/arch/arm/isa.cc Mon Nov 15 14:04:04 2010 -0600
@@ -173,11 +173,10 @@
cpsr.t = pc.thumb() ? 1 : 0;
return cpsr;
}
- if (misc_reg >= MISCREG_CP15_UNIMP_START &&
- misc_reg < MISCREG_CP15_END) {
+ if (misc_reg >= MISCREG_CP15_UNIMP_START)
panic("Unimplemented CP15 register %s read.\n",
miscRegName[misc_reg]);
- }
+
switch (misc_reg) {
case MISCREG_CLIDR:
warn_once("The clidr register always reports 0 caches.\n");
diff -r 846fb3ffe0dc -r d7360f5052b2 src/arch/arm/isa/formats/misc.isa
--- a/src/arch/arm/isa/formats/misc.isa Mon Nov 15 14:04:04 2010 -0600
+++ b/src/arch/arm/isa/formats/misc.isa Mon Nov 15 14:04:04 2010 -0600
@@ -180,6 +180,10 @@
// Read/write, priveleged only.
default:
+ if (miscReg >= MISCREG_CP15_UNIMP_START)
+ return new FailUnimplemented(csprintf("%s %s",
+ isRead ? "mrc" : "mcr", miscRegName[miscReg]).c_str(),
+ machInst);
if (isRead) {
return new Mrc15(machInst, rt, (IntRegIndex)miscReg);
} else {
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