changeset 28a677d7cb51 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=28a677d7cb51
description:
O3: prevent a squash when completeAcc() modifies misc reg through TC.
This happens on ARM instructions when they update the IT state bits.
Code and associated comment was copied from execute() and initiateAcc()
methods
diffstat:
src/cpu/o3/dyn_inst_impl.hh | 9 +++++++++
1 files changed, 9 insertions(+), 0 deletions(-)
diffs (21 lines):
diff -r d7360f5052b2 -r 28a677d7cb51 src/cpu/o3/dyn_inst_impl.hh
--- a/src/cpu/o3/dyn_inst_impl.hh Mon Nov 15 14:04:04 2010 -0600
+++ b/src/cpu/o3/dyn_inst_impl.hh Mon Nov 15 14:04:04 2010 -0600
@@ -113,8 +113,17 @@
Fault
BaseO3DynInst<Impl>::completeAcc(PacketPtr pkt)
{
+ // @todo: Pretty convoluted way to avoid squashing from happening
+ // when using the TC during an instruction's execution
+ // (specifically for instructions that have side-effects that use
+ // the TC). Fix this.
+ bool in_syscall = this->thread->inSyscall;
+ this->thread->inSyscall = true;
+
this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);
+ this->thread->inSyscall = in_syscall;
+
return this->fault;
}
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